96 lines
4.3 KiB
Verilog
96 lines
4.3 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// DES ////
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//// DES Top Level module ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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module des(desOut, desIn, key, decrypt, roundSel, clk);
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output [63:0] desOut;
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input [63:0] desIn;
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input [55:0] key;
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input decrypt;
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input [3:0] roundSel;
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input clk;
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wire [1:48] K_sub;
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wire [1:64] IP, FP;
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reg [1:32] L, R;
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wire [1:32] Xin;
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wire [1:32] Lout, Rout;
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wire [1:32] out;
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assign Lout = (roundSel == 0) ? IP[33:64] : R;
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assign Xin = (roundSel == 0) ? IP[01:32] : L;
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assign Rout = Xin ^ out;
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assign FP = { Rout, Lout};
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crp u0( .P(out), .R(Lout), .K_sub(K_sub) );
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always @(posedge clk)
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L <= #1 Lout;
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always @(posedge clk)
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R <= #1 Rout;
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// Select a subkey from key.
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key_sel u1(
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.K_sub( K_sub ),
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.K( key ),
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.roundSel( roundSel ),
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.decrypt( decrypt )
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);
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// Perform initial permutation
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assign IP[1:64] = { desIn[06], desIn[14], desIn[22], desIn[30], desIn[38], desIn[46],
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desIn[54], desIn[62], desIn[04], desIn[12], desIn[20], desIn[28],
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desIn[36], desIn[44], desIn[52], desIn[60], desIn[02], desIn[10],
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desIn[18], desIn[26], desIn[34], desIn[42], desIn[50], desIn[58],
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desIn[00], desIn[08], desIn[16], desIn[24], desIn[32], desIn[40],
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desIn[48], desIn[56], desIn[07], desIn[15], desIn[23], desIn[31],
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desIn[39], desIn[47], desIn[55], desIn[63], desIn[05], desIn[13],
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desIn[21], desIn[29], desIn[37], desIn[45], desIn[53], desIn[61],
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desIn[03], desIn[11], desIn[19], desIn[27], desIn[35], desIn[43],
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desIn[51], desIn[59], desIn[01], desIn[09], desIn[17], desIn[25],
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desIn[33], desIn[41], desIn[49], desIn[57] };
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// Perform final permutation
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assign desOut = { FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32],
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FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31],
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FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30],
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FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29],
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FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28],
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FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
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FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26],
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FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };
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endmodule
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