45 lines
1.1 KiB
ReStructuredText
45 lines
1.1 KiB
ReStructuredText
.. _file_format_bus_group_file:
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Bus Group File (.xml)
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=====================
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The bus group file aims to show
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- How bus ports are flatten by EDA engines, e.g., synthesis.
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- What are the pins in post-routing corresponding to the bus ports before synthesis
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An example of file is shown as follows.
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.. code-block:: xml
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<bus_group>
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<bus name="i_addr[0:3]" big_endian="false">
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<pin id="0" name="i_addr_0_"/>
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<pin id="1" name="i_addr_1_"/>
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<pin id="2" name="i_addr_2_"/>
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<pin id="3" name="i_addr_3_"/>
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</bus>
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</bus_group>
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Bus-related Syntax
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------------------
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.. option:: name="<string>"
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The bus port defined before synthesis, e.g., addr[0:3]
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.. option:: big_endian="<bool>"
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Specify if this port should follow big endian or little endian in Verilog netlist. By default, big endian is assumed, e.g., addr[0:3].
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Pin-related Syntax
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------------------
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.. option:: id="<int>"
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The index of the current pin in a bus port. The index must be the range of **[LSB, MSB-1]** that are defined in the bus.
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.. option:: name="<string>"
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The pin name after bus flatten in synthesis results
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