Lalit Sharma 7945628307 Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification		2021-03-07 22:25:01 -08:00
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bitstream_annotation.xml	[Test] Add LUT adder test using quicklogic synthesis script	2021-02-23 16:50:58 -07:00
task.conf	Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification	2021-03-07 22:25:01 -08:00