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OpenFPGA/openfpga_flow/openfpga_cell_library
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tangxifan 22e675148e [HDL] Add HDL codes for a super LUT with embedded carry logic 2021-02-09 21:13:22 -07:00
..
spice [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
spice_testbench [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
verilog [HDL] Add HDL codes for a super LUT with embedded carry logic 2021-02-09 21:13:22 -07:00
verilog_testbench [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00