193 lines
6.7 KiB
C++
193 lines
6.7 KiB
C++
/********************************************************************
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* This file includes the top-level function of this library
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* which reads an XML modeling OpenFPGA architecture to the associated
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* data structures
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*******************************************************************/
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#include <string>
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/* Headers from pugi XML library */
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#include "pugixml.hpp"
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#include "pugixml_util.hpp"
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/* Headers from vtrutil library */
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#include "vtr_time.h"
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/* Headers from libarchfpga */
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#include "arch_error.h"
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#include "openfpga_arch_linker.h"
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#include "read_xml_bitstream_setting.h"
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#include "read_xml_circuit_library.h"
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#include "read_xml_config_protocol.h"
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#include "read_xml_openfpga_arch.h"
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#include "read_xml_pb_type_annotation.h"
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#include "read_xml_routing_circuit.h"
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#include "read_xml_simulation_setting.h"
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#include "read_xml_technology_library.h"
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#include "read_xml_tile_annotation.h"
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#include "read_xml_util.h"
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/********************************************************************
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* Top-level function to parse an XML file and load data to :
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* 1. circuit library
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*******************************************************************/
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openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
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vtr::ScopedStartFinishTimer timer("Read OpenFPGA architecture");
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openfpga::Arch openfpga_arch;
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pugi::xml_node Next;
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/* Parse the file */
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pugi::xml_document doc;
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pugiutil::loc_data loc_data;
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try {
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loc_data = pugiutil::load_xml(doc, arch_file_name);
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/* First node should be <openfpga_architecture> */
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auto xml_openfpga_arch =
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get_single_child(doc, "openfpga_architecture", loc_data);
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/* Parse circuit_models to circuit library
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* under the node <module_circuit_models>
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*/
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auto xml_circuit_models =
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get_single_child(xml_openfpga_arch, "circuit_library", loc_data);
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openfpga_arch.circuit_lib =
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read_xml_circuit_library(xml_circuit_models, loc_data);
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/* Automatically identify the default models for circuit library */
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openfpga_arch.circuit_lib.auto_detect_default_models();
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/* Build the internal links for the circuit library */
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openfpga_arch.circuit_lib.build_model_links();
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/* Build the timing graph inside the circuit library */
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openfpga_arch.circuit_lib.build_timing_graphs();
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/* Parse technology library */
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auto xml_tech_lib =
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get_single_child(xml_openfpga_arch, "technology_library", loc_data);
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openfpga_arch.tech_lib =
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read_xml_technology_library(xml_tech_lib, loc_data);
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/* Build the internal link for technology library */
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openfpga_arch.tech_lib.link_models_to_variations();
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/* Binding circuit models to device models */
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bind_circuit_model_to_technology_model(openfpga_arch);
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/* Parse configuration protocol to data structure */
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openfpga_arch.config_protocol =
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read_xml_config_protocol(xml_openfpga_arch, loc_data);
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/* Build the internal link between configuration protocol and circuit
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* library */
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link_config_protocol_to_circuit_library(openfpga_arch);
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/* Now, we can know the default configurable memory model
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* Apply it to all the SRAM ports of circuit models
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*/
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config_circuit_models_sram_port_to_default_sram_model(
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openfpga_arch.circuit_lib, openfpga_arch.config_protocol.memory_model());
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/* Parse the connection block circuit definition */
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openfpga_arch.cb_switch2circuit = read_xml_cb_switch_circuit(
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xml_openfpga_arch, loc_data, openfpga_arch.circuit_lib);
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/* Parse the connection block circuit definition */
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openfpga_arch.cb_switch2circuit = read_xml_cb_switch_circuit(
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xml_openfpga_arch, loc_data, openfpga_arch.circuit_lib);
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/* Parse the switch block circuit definition */
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openfpga_arch.sb_switch2circuit = read_xml_sb_switch_circuit(
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xml_openfpga_arch, loc_data, openfpga_arch.circuit_lib);
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/* Parse the routing segment circuit definition */
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openfpga_arch.routing_seg2circuit = read_xml_routing_segment_circuit(
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xml_openfpga_arch, loc_data, openfpga_arch.circuit_lib);
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/* Parse the direct circuit definition */
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openfpga_arch.arch_direct = read_xml_direct_circuit(
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xml_openfpga_arch, loc_data, openfpga_arch.circuit_lib);
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/* Parse the pb_type annotation */
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openfpga_arch.tile_annotations =
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read_xml_tile_annotations(xml_openfpga_arch, loc_data);
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/* Parse the pb_type annotation */
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openfpga_arch.pb_type_annotations =
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read_xml_pb_type_annotations(xml_openfpga_arch, loc_data);
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} catch (pugiutil::XmlError& e) {
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archfpga_throw(arch_file_name, e.line(), "%s", e.what());
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}
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return openfpga_arch;
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}
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/********************************************************************
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* Top-level function to parse an XML file and load data to simulation settings
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*******************************************************************/
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openfpga::SimulationSetting read_xml_openfpga_simulation_settings(
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const char* sim_setting_file_name) {
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vtr::ScopedStartFinishTimer timer("Read OpenFPGA simulation settings");
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openfpga::SimulationSetting openfpga_sim_setting;
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pugi::xml_node Next;
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/* Parse the file */
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pugi::xml_document doc;
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pugiutil::loc_data loc_data;
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try {
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loc_data = pugiutil::load_xml(doc, sim_setting_file_name);
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/* Second node should be <openfpga_simulation_setting> */
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auto xml_simulation_settings =
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get_single_child(doc, "openfpga_simulation_setting", loc_data);
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/* Parse simulation settings to data structure */
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openfpga_sim_setting =
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read_xml_simulation_setting(xml_simulation_settings, loc_data);
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} catch (pugiutil::XmlError& e) {
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archfpga_throw(sim_setting_file_name, e.line(), "%s", e.what());
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}
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return openfpga_sim_setting;
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}
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/********************************************************************
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* Top-level function to parse an XML file and load data to bitstream settings
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*******************************************************************/
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openfpga::BitstreamSetting read_xml_openfpga_bitstream_settings(
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const char* bitstream_setting_file_name) {
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vtr::ScopedStartFinishTimer timer("Read OpenFPGA bitstream settings");
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openfpga::BitstreamSetting openfpga_bitstream_setting;
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pugi::xml_node Next;
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/* Parse the file */
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pugi::xml_document doc;
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pugiutil::loc_data loc_data;
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try {
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loc_data = pugiutil::load_xml(doc, bitstream_setting_file_name);
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/* Second node should be <openfpga_simulation_setting> */
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auto xml_bitstream_settings =
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get_single_child(doc, "openfpga_bitstream_setting", loc_data);
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/* Parse simulation settings to data structure */
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openfpga_bitstream_setting =
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read_xml_bitstream_setting(xml_bitstream_settings, loc_data);
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} catch (pugiutil::XmlError& e) {
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archfpga_throw(bitstream_setting_file_name, e.line(), "%s", e.what());
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}
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return openfpga_bitstream_setting;
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}
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