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behavioral_verilog/config
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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bram
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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duplicated_grid_pin/config
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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fabric_chain
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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fixed_simulation_settings/config
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add new test cases about user-defined simulation settings
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2020-06-11 19:31:03 -06:00 |
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flatten_routing/config
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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full_testbench
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deploy read_openfpga_simulation_setting in CI on a single test case
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2020-06-11 19:31:16 -06:00 |
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generate_fabric/config
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add testcases on generate fabric/testbench only
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2020-06-11 19:31:01 -06:00 |
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generate_testbench/config
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add testcases on generate fabric/testbench only
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2020-06-11 19:31:01 -06:00 |
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hard_adder/config
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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implicit_verilog/config
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start using counter benchmark in regression tests
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2020-06-11 19:31:15 -06:00 |
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io
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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lut_design
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add more test cases about LUT design and deploy to CI
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2020-06-11 19:31:02 -06:00 |
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mcnc_big20/config
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start testing mcnc_big20 using OpenFPGA tasks
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2020-06-11 19:30:55 -06:00 |
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mux_design
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add local encoder test case
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2020-06-11 19:31:01 -06:00 |
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preconfig_testbench
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add preconfig testbench test case for memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
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sdc_time_unit/config
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fix the broken CI/regression tests due to incorrect file path
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2020-06-11 19:31:10 -06:00 |
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spypad/config
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try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
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2020-06-11 19:31:01 -06:00 |
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untileable/config
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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