OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream
tangxifan 17bc7fc296 update Verilog generator to use GSB data structure. SDC generator and TCL generator to go 2019-06-08 20:11:22 -06:00
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fpga_bitstream.c updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
fpga_bitstream.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
fpga_bitstream_pbtypes.c Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
fpga_bitstream_pbtypes.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
fpga_bitstream_primitives.c Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
fpga_bitstream_primitives.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
fpga_bitstream_routing.c update Verilog generator to use GSB data structure. SDC generator and TCL generator to go 2019-06-08 20:11:22 -06:00
fpga_bitstream_routing.h updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00