131 lines
3.8 KiB
ReStructuredText
131 lines
3.8 KiB
ReStructuredText
Fabric-dependent Bitstream
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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Usage
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`````
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Fabric-dependent bitstream is design to be loadable to the configuration protocols of FPGAs.
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The bitstream just sets an order to the configuration bits in the database, without duplicating the database.
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OpenFPGA framework provides a fabric-dependent bitstream generator which is aligned to our Verilog netlists.
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The fabric-dependent bitstream can be found in the pre-configured Verilog testbenches.
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The fabric bitsteam can be outputted in different file format in terms of usage.
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Plain Text File Format
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```````````````````````
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This file format is designed to be directly loaded to an FPGA fabric.
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It does not include any comments but only bitstream.
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The information depends on the type of configuration procotol.
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.. option:: vanilla
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A line consisting of ``0``|``1``
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.. option:: scan_chain
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A line consisting of ``0``|``1``
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.. option:: memory_bank
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Multiple lines will be included, each of which is organized as <address><space><bit>.
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Note that due to the use of Bit-Line and Word-Line decoders, every two lines are paired.
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The first line represents the Bit-Line address and configuration bit.
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The second line represents the Word-Line address and configuration bit.
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For example
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.. code_block::
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<bitline_address> <bit_value>
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<wordline_address> <bit_value>
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<bitline_address> <bit_value>
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<wordline_address> <bit_value>
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...
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<bitline_address> <bit_value>
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<wordline_address> <bit_value>
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.. option:: frame_based
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Multiple lines will be included, each of which is organized as <address><space><bit>.
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For example
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.. code_block::
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<frame_address> <bit_value>
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<frame_address> <bit_value>
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...
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<frame_address> <bit_value>
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XML File Format
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```````````````
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This file format is designed to generate testbenches using external tools, e.g., CocoTB.
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In principle, the file consist a number of XML node ``<bit>``, each bit contains the following attributes:
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- ``id``: The unique id of the configuration bit in the fabric bitstream.
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- ``value``: The configuration bit value.
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- ``hierarchy`` represents the location of this block in FPGA fabric.
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The hierachy includes the full hierarchy of this block
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- ``instance`` denotes the instance name which you can find in the fabric netlists
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- ``level`` denotes the depth of the block in the hierarchy
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A quick example:
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.. code_block:: xml
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<bit id="0" value="1">
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<hierarchy>
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<instance level="0" name="fpga_top"/>
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<instance level="1" name="grid_clb_1__2_"/>
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<instance level="2" name="logical_tile_clb_mode_clb__0"/>
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<instance level="3" name="mem_fle_9_in_5"/>
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</hierarchy>
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</bit>
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Other information may depend on the type of configuration procotol.
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.. option:: memory_bank
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- ``bl``: Bit line address information
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- ``wl``: Word line address information
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A quick example:
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.. code_block:: xml
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<bit id="0" value="1">
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<hierarchy>
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<instance level="0" name="fpga_top"/>
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<instance level="1" name="grid_io_bottom_1__0_"/>
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<instance level="2" name="logical_tile_io_mode_io__0"/>
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<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
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<instance level="4" name="iopad_sram_blwl_mem"/>
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</hierarchy>
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<bl address="000000"/>
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<wl address="000000"/>
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</bit>
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.. option:: frame_based
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- ``frame``: frame address information
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A quick example:
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.. code_block:: xml
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<bit id="0" value="1">
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<hierarchy>
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<instance level="0" name="fpga_top"/>
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<instance level="1" name="grid_io_bottom_1__0_"/>
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<instance level="2" name="logical_tile_io_mode_io__0"/>
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<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
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<instance level="4" name="iopad_config_latch_mem"/>
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</hierarchy>
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<frame address="0000000000000000"/>
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</bit>
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