Laboratory for Nano Integrated Systems (LNIS) 16128f0905 Merge pull request #107 from LNIS-Projects/dev ... Enable Customized Fabric Netlist Location in Verilog Testbench Generation		2020-10-12 13:47:40 -06:00
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OpenFPGAShellScripts	[Flow] bug fix in the sample script for fabric netlist customization	2020-10-12 12:52:01 -06:00
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Bug fix in the and2_or2 benchmark	2020-09-17 10:35:13 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Edits to enable basic run_fpga_flow.py	2020-10-02 10:18:10 -04:00
openfpga_arch	[Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes	2020-10-10 20:24:57 -06:00
openfpga_cell_library	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
openfpga_simulation_settings	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00
scripts	Merge pull request #104 from lukefahr/disp_fix	2020-10-07 09:54:06 -06:00
tasks	[Test] Now use a light architecture to speed up the test case runtime	2020-10-12 12:53:34 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Architecture] Add k4 series architecture using pattern-based local routing	2020-09-23 16:05:39 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00