206 lines
8.2 KiB
C++
206 lines
8.2 KiB
C++
/***************************************************************************************
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* Output internal structure of DeviceRRGSB to XML format
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***************************************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_log.h"
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#include "vtr_assert.h"
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#include "vtr_time.h"
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/* Headers from openfpgautil library */
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#include "openfpga_side_manager.h"
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#include "openfpga_digest.h"
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#include "openfpga_naming.h"
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#include "openfpga_rr_graph_utils.h"
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#include "write_xml_device_rr_gsb.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/***************************************************************************************
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* Output internal structure (only the switch block part) of a RRGSB to XML format
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***************************************************************************************/
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static
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void write_rr_switch_block_to_xml(const std::string fname_prefix,
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const RRGraph& rr_graph,
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const RRGSB& rr_gsb,
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const bool& verbose) {
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/* Prepare file name */
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std::string fname(fname_prefix);
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vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
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fname += generate_switch_block_module_name(gsb_coordinate);
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fname += ".xml";
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VTR_LOGV(verbose,
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"Output internal structure of Switch Block to '%s'\n",
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fname.c_str());
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/* Create a file handler*/
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std::fstream fp;
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/* Open a file */
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fp.open(fname, std::fstream::out | std::fstream::trunc);
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/* Validate the file stream */
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check_file_stream(fname.c_str(), fp);
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/* Output location of the Switch Block */
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fp << "<rr_gsb x=\"" << rr_gsb.get_x() << "\" y=\"" << rr_gsb.get_y() << "\""
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<< " num_sides=\"" << rr_gsb.get_num_sides() << "\">" << std::endl;
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/* Output each side */
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for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
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SideManager gsb_side_manager(side);
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enum e_side gsb_side = gsb_side_manager.get_side();
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/* Output IPIN nodes */
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for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(gsb_side); ++inode) {
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const RRNodeId& cur_rr_node = rr_gsb.get_ipin_node(gsb_side, inode);
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/* General information of this IPIN */
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fp << "\t<" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
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<< " side=\"" << gsb_side_manager.to_string()
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<< "\" index=\"" << inode
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<< "\" mux_size=\"" << get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node).size()
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<< "\">"
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<< std::endl;
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/* General information of each driving nodes */
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for (const RRNodeId& driver_node : get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node)) {
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/* Skip OPINs: they should be in direct connections */
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if (OPIN == rr_graph.node_type(driver_node)) {
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continue;
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}
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enum e_side chan_side = rr_gsb.get_cb_chan_side(gsb_side);
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SideManager chan_side_manager(chan_side);
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/* For channel node, we do not know the node direction
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* But we are pretty sure it is either IN_PORT or OUT_PORT
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* So we just try and find what is valid
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*/
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int driver_node_index = rr_gsb.get_chan_node_index(chan_side, driver_node);
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/* We must have a valide node index */
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VTR_ASSERT(-1 != driver_node_index);
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const RRSegmentId& des_segment_id = rr_gsb.get_chan_node_segment(chan_side, driver_node_index);
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fp << "\t\t<driver_node type=\"" << rr_node_typename[rr_graph.node_type(driver_node)]
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<< "\" side=\"" << chan_side_manager.to_string()
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<< "\" index=\"" << driver_node_index
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<< "\" segment_id=\"" << size_t(des_segment_id)
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<< "\"/>"
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<< std::endl;
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}
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fp << "\t</" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
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<< ">"
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<< std::endl;
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}
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/* Output chan nodes */
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for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) {
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/* We only care OUT_PORT */
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if (OUT_PORT != rr_gsb.get_chan_node_direction(gsb_side, inode)) {
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continue;
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}
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/* Output drivers */
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const RRNodeId& cur_rr_node = rr_gsb.get_chan_node(gsb_side, inode);
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std::vector<RREdgeId> driver_rr_edges = rr_gsb.get_chan_node_in_edges(rr_graph, gsb_side, inode);
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/* Output node information: location, index, side */
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const RRSegmentId& src_segment_id = rr_gsb.get_chan_node_segment(gsb_side, inode);
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/* Check if this node is directly connected to the node on the opposite side */
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if (true == rr_gsb.is_sb_node_passing_wire(rr_graph, gsb_side, inode)) {
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driver_rr_edges.clear();
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}
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fp << "\t<" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
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<< " side=\"" << gsb_side_manager.to_string()
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<< "\" index=\"" << inode
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<< "\" segment_id=\"" << size_t(src_segment_id)
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<< "\" mux_size=\"" << driver_rr_edges.size()
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<< "\">"
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<< std::endl;
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/* Direct connection: output the node on the opposite side */
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if (0 == driver_rr_edges.size()) {
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SideManager oppo_side = gsb_side_manager.get_opposite();
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fp << "\t\t<driver_node type=\"" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
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<< "\" side=\"" << oppo_side.to_string()
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<< "\" index=\"" << rr_gsb.get_node_index(rr_graph, cur_rr_node, oppo_side.get_side(), IN_PORT)
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<< "\" segment_id=\"" << size_t(src_segment_id)
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<< "\"/>"
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<< std::endl;
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} else {
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for (const RREdgeId& driver_rr_edge : driver_rr_edges) {
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const RRNodeId& driver_rr_node = rr_graph.edge_src_node(driver_rr_edge);
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e_side driver_node_side = NUM_SIDES;
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int driver_node_index = -1;
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rr_gsb.get_node_side_and_index(rr_graph, driver_rr_node, IN_PORT, driver_node_side, driver_node_index);
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VTR_ASSERT(-1 != driver_node_index);
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SideManager driver_side(driver_node_side);
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if (OPIN == rr_graph.node_type(driver_rr_node)) {
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SideManager grid_side(rr_graph.node_side(driver_rr_node));
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fp << "\t\t<driver_node type=\"" << rr_node_typename[OPIN]
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<< "\" side=\"" << driver_side.to_string()
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<< "\" index=\"" << driver_node_index
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<< "\" grid_side=\"" << grid_side.to_string()
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<<"\"/>"
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<< std::endl;
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} else {
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const RRSegmentId& des_segment_id = rr_gsb.get_chan_node_segment(driver_node_side, driver_node_index);
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fp << "\t\t<driver_node type=\"" << rr_node_typename[rr_graph.node_type(driver_rr_node)]
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<< "\" side=\"" << driver_side.to_string()
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<< "\" index=\"" << driver_node_index
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<< "\" segment_id=\"" << size_t(des_segment_id)
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<< "\"/>"
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<< std::endl;
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}
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}
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}
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fp << "\t</" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
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<< ">"
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<< std::endl;
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}
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}
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fp << "</rr_gsb>"
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<< std::endl;
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/* close a file */
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fp.close();
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}
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/***************************************************************************************
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* Output internal structure (only the switch block part) of all the RRGSBs
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* in a DeviceRRGSB to XML format
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***************************************************************************************/
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void write_device_rr_gsb_to_xml(const char* sb_xml_dir,
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const RRGraph& rr_graph,
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const DeviceRRGSB& device_rr_gsb,
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const bool& verbose) {
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std::string xml_dir_name = format_dir_path(std::string(sb_xml_dir));
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/* Create directories */
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create_directory(xml_dir_name);
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vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
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size_t gsb_counter = 0;
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/* For each switch block, an XML file will be outputted */
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for (size_t ix = 0; ix < sb_range.x(); ++ix) {
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for (size_t iy = 0; iy < sb_range.y(); ++iy) {
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const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
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write_rr_switch_block_to_xml(xml_dir_name, rr_graph, rr_gsb, verbose);
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gsb_counter++;
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}
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}
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VTR_LOG("Output %lu XML files to directory '%s'\n",
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gsb_counter,
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xml_dir_name.c_str());
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}
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} /* end namespace openfpga */
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