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tangxifan 7729f671ab [Regression Tests] Remove deadlink 2020-09-22 18:35:41 -06:00
..
basic_tests [Regression tests] Add test case for the k4n4 with fracturable 32-bit multiplier 2020-09-22 15:32:54 -06:00
benchmark_sweep update task files using the new syntax on SHELL variables 2020-07-27 15:25:49 -06:00
compilation_verification/config update task files using the new syntax on SHELL variables 2020-07-27 15:25:49 -06:00
fpga_bitstream [Regression Tests] Now use fixed device layout in test cases for best coverage 2020-09-21 18:44:13 -06:00
fpga_sdc/sdc_time_unit/config classify regression test to dedicated categories 2020-07-27 17:18:59 -06:00
fpga_spice/generate_spice/config add load architecture bitstream test case and reorganize regression tests in category of openfpga tools 2020-07-27 15:54:46 -06:00
fpga_verilog [Regression test] Remove no local routing from fpga verilog tests 2020-09-22 11:48:19 -06:00
mcnc_big20/config update task files using the new syntax on SHELL variables 2020-07-27 15:25:49 -06:00
.gitignore Added gitignore to skip run directory tracking 2019-08-19 19:06:01 -06:00
README.md add README to explain the organization of regression tests 2020-07-28 13:44:06 -06:00

README.md

Regression tests for OpenFPGA

The regression tests are grouped in category of OpenFPGA tools as well as integrated flows. The principle is that each OpenFPGA tool should have a set of regression tests.

  • compilation_verfication: a quicktest after compilation

  • Basic regression tests should focus on fundamental flow integration, such as

    • Yosys + VPR + OpenFPGA for a Verilog-to-Verification flow-run

  • FPGA-Verilog regression tests should focus on testing fabric correctness, such as

    • VPR + OpenFPGA integration for a BLIF-to-Verification flow-run

  • FPGA-Bitstream regression tests should focus on testing bitstream correctness and runtime on large devices and benchmark suites

  • FPGA-SDC regression test should focus on SDC file generation and necessary syntax check

  • FPGA-SPICE regression test should focus on SPICE netlist generation / compilation and SPICE simulations qwith QoR checks.

Please keep this README up-to-date on the OpenFPGA tools