36 lines
1017 B
Verilog
36 lines
1017 B
Verilog
//-----------------------------------------------------
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// Design Name : mult_32x32
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// File Name : mult_32x32.v
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// Function : A 32-bit multiplier which can operate in fracturable modes:
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// 1. four 8-bit multipliers
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// 2. two 16-bit multipliers
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// 3. one 32-bit multipliers
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// Coder : Xifan Tang
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//-----------------------------------------------------
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module mult_32x32 (
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input [0:31] a,
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input [0:31] b,
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output [0:63] out,
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input [0:1] mode);
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reg [0:63] out_reg;
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always @(mode, a, b) begin
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if (2'b01 == mode) begin
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out_reg[0:15] <= a[0:7] * b[0:7];
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out_reg[16:31] <= a[8:15] * b[8:15];
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out_reg[32:47] <= a[16:23] * b[16:23];
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out_reg[48:63] <= a[24:31] * b[24:31];
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end else if (2'b10 == mode) begin
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out_reg[0:31] <= a[0:15] * b[0:15];
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out_reg[32:63] <= a[16:31] * b[16:31];
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end else begin
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out_reg <= a * b;
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end
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end
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assign out = out_reg;
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endmodule
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