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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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14726e9317
OpenFPGA
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openfpga_flow
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benchmarks
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micro_benchmark
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adder
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adder_8
History
tangxifan
a898537474
[Benchmark] Remove redundant post-synthesis netlist for ``adder_8``
2021-06-30 15:29:13 -06:00
..
adder_8.act
[Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders
2021-06-30 15:13:47 -06:00
adder_8.eblif
[Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders
2021-06-30 15:13:47 -06:00
adder_8.v
[Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders
2021-06-30 15:13:47 -06:00
adder_8_out.v
[Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders
2021-06-30 15:13:47 -06:00