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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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1445d5db0a
OpenFPGA
/
openfpga_flow
/
openfpga_cell_library
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tangxifan
62a437a3a1
Merge branch 'master' into patch-3
2022-10-21 09:41:26 -07:00
..
spice
[Architecture] Reorganize the cell netlists and update architecture files accordingly
2020-09-25 11:55:28 -06:00
spice_testbench
[Architecture] Reorganize the cell netlists and update architecture files accordingly
2020-09-25 11:55:28 -06:00
verilog
Merge branch 'master' into patch-3
2022-10-21 09:41:26 -07:00
verilog_testbench
[Architecture] Reorganize the cell netlists and update architecture files accordingly
2020-09-25 11:55:28 -06:00
Makefile
[test] add regression test to validate compilation of openfpga cell library files
2022-05-09 16:00:51 +08:00
verilog_sources.f
[test] add regression test to validate compilation of openfpga cell library files
2022-05-09 16:00:51 +08:00