48 lines
1.2 KiB
Verilog
48 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 05/03/2021 04:52:18 PM
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// Design Name:
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// Module Name: reset_generator
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module reset_generator(
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input clk,
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output reg pulse
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);
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parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value
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parameter ACTIVE_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied
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reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter;
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initial begin
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pulse <= INITIAL_VALUE;
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active_cycle_counter <= 0;
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end
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// Wait a number of clock cycles, hold the initial value
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always @(posedge clk) begin
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if (active_cycle_counter == ACTIVE_CYCLES) begin
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pulse <= ~INITIAL_VALUE;
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end else begin
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active_cycle_counter <= active_cycle_counter + 1;
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end
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end
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endmodule
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