98 lines
4.8 KiB
ReStructuredText
98 lines
4.8 KiB
ReStructuredText
.. _fpga_verilog_testbench:
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Testbench
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---------
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In this part, we will introduce the hierarchy, dependency and functionality of each Verilog testbench, which are generated to verify a FPGA fabric implemented with an application.
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+-----------------+---------+----------------+---------------+
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| Testbench Type | Runtime | Test Vector | Test Coverage |
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+=================+=========+================+===============+
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| Full | Long | Random Stimuli | Full fabric |
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+-----------------+---------+----------------+---------------+
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| Formal-oriented | Short | Random Stimuli | Programmable |
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| | | | fabric only |
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| | | Formal Method | |
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+-----------------+---------+----------------+---------------+
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OpenFPGA can auto-generate two types of Verilog testbenches to validate the correctness of the fabric: full and formal-oriented.
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Both testbenches share the same organization, as depicted in :numref:`fig_verilog_testbench_organization`.
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To enable self-testing, the FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag.
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.. _fig_verilog_testbench_organization:
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.. figure:: figures/full_testbench_block_diagram.svg
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:width: 100%
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:alt: Verilog testbench principles
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Principles of Verilog testbenches: (1) using common input stimuli; (2) applying bitstream; (3) checking output vectors.
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.. _fig_verilog_full_testbench_waveform:
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.. figure:: figures/full_testbench_waveform.svg
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:width: 100%
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:alt: Full testbench waveform
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Illustration on the waveforms in full testbench
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Full Testbench
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~~~~~~~~~~~~~~
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Full testbench aims at simulating an entire FPGA operating period, consisting of two phases:
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- the **Configuration Phase**, where the synthesized design bitstream is loaded to the programmable fabric, as highlighted by the green rectangle of :numref:`fig_verilog_full_testbench_waveform`;
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- the **Operating Phase**, where random input vectors are auto-generated to drive both Devices Under Test (DUTs), as highlighted by the red rectangle of :numref:`fig_verilog_full_testbench_waveform`. Using the full testbench, users can validate both the configuration circuits and programming fabric of an FPGA.
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Formal-oriented Testbench
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~~~~~~~~~~~~~~~~~~~~~~~~~
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The formal-oriented testbench aims to test a programmed FPGA is instantiated with the user's bitstream.
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The module of the programmed FPGA is encapsulated with the same port mapping as the user's RTL design and thus can be fed to a formal tool for a 100% coverage formal verification. Compared to the full testbench, this skips the time-consuming configuration phase, reducing the simulation time, potentially also significantly accelerating the functional verification, especially for large FPGAs.
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.. warning:: Formal-oriented testbenches do not validate the configuration protocol of FPGAs. It is used to validate FPGA with a wide range of benchmarks.
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General Usage
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~~~~~~~~~~~~~
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All the generated Verilog testbenches are located in the directory as you specify in the OpenFPGA command ``write_fabric_verilog``.
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Inside the directory, the Verilog testbenches are organized as illustrated in :numref:`fig_verilog_testbench_hierarchy`.
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.. _fig_verilog_testbench_hierarchy:
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.. figure:: ./figures/verilog_testbench_hierarchy.svg
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:width: 100%
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Hierarchy of Verilog testbenches for a FPGA fabric implemented with an application
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.. note:: ``<bench_name>`` is the module name of users' RTL design.
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.. option:: <bench_name>_include_netlist.v
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This file includes all the related Verilog netlists that are used by the testbenches, including both full and formal oriented testbenches.
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This file is created to simplify the netlist addition for HDL simulator.
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This is the only file you need to add to a simulator.
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.. note:: Fabric Verilog netlists are included in this file.
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.. option:: <bench_name>_autocheck_top_tb.v
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This is the netlist for full testbench.
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.. option:: <bench_name>_formal_random_top_tb.v
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This is the netlist for formal-oriented testbench.
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.. option:: <bench_name>_top_formal_verification.v
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This netlist includes a Verilog module of a pre-configured FPGA fabric, which is a wrapper on top of the ``fpga_top.v`` netlist.
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The wrapper module has the same port map as the top-level module of user's RTL design, which be directly def to formal verification tools to validate FPGA's functional equivalence.
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:numref:`fig_preconfig_module` illustrates the organization of a pre-configured module, which consists of a FPGA fabric (see :ref:`fabric_netlists`) and a hard-coded bitstream.
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Only used I/Os of FPGA fabric will appear in the port list of the pre-configured module.
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.. _fig_preconfig_module:
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.. figure:: ./figures/preconfig_module.png
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:width: 100%
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Internal structure of a pre-configured FPGA module
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