7494 lines
395 KiB
XML
7494 lines
395 KiB
XML
<technology file="winbond_tech.sp" size="100n">
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<operating_point temperature="25" Vdd="1.2"/>
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<p_to_n ratio="2.3"/>
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<transistor type="nmos">
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<long_size W="1" L="2">
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<leakage_current subthreshold="26.0715p"/>
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<capacitance C_g="358.0419a" C_s="331.3444a" C_d="331.8299a"/>
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</long_size>
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<size W="1.00" L="1">
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<leakage_current subthreshold="102.5911p" gate="926.2268f"/>
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<capacitance C_g="200.8734a" C_s="245.7515a" C_d="245.8916a"/>
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</size>
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<size W="1.05" L="1">
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<leakage_current subthreshold="106.2108p" gate="978.2039f"/>
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<capacitance C_g="210.9139a" C_s="256.5574a" C_d="256.7050a"/>
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</size>
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<size W="1.10" L="1">
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<leakage_current subthreshold="109.9385p" gate="1.0305p"/>
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<capacitance C_g="220.9546a" C_s="267.3633a" C_d="267.5185a"/>
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</size>
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<size W="1.16" L="1">
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<leakage_current subthreshold="114.5367p" gate="1.0935p"/>
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<capacitance C_g="233.0036a" C_s="280.3304a" C_d="280.4947a"/>
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</size>
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<size W="1.22" L="1">
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<leakage_current subthreshold="119.2539p" gate="1.1569p"/>
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<capacitance C_g="245.0528a" C_s="293.2975a" C_d="293.4710a"/>
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</size>
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<size W="1.28" L="1">
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<leakage_current subthreshold="124.0754p" gate="1.2206p"/>
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<capacitance C_g="257.1022a" C_s="306.2646a" C_d="306.4473a"/>
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</size>
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<size W="1.34" L="1">
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<leakage_current subthreshold="128.9890p" gate="1.2845p"/>
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<capacitance C_g="269.1517a" C_s="319.2316a" C_d="319.4237a"/>
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</size>
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<size W="1.41" L="1">
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<leakage_current subthreshold="134.8244p" gate="1.3594p"/>
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<capacitance C_g="283.2097a" C_s="334.3599a" C_d="334.5629a"/>
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</size>
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<size W="1.48" L="1">
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<leakage_current subthreshold="140.7578p" gate="1.4346p"/>
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<capacitance C_g="297.2679a" C_s="349.4881a" C_d="349.7022a"/>
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</size>
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<size W="1.55" L="1">
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<leakage_current subthreshold="146.7781p" gate="1.5101p"/>
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<capacitance C_g="311.3262a" C_s="364.6163a" C_d="364.8415a"/>
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</size>
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<size W="1.63" L="1">
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<leakage_current subthreshold="153.7527p" gate="1.5966p"/>
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<capacitance C_g="327.3930a" C_s="381.9056a" C_d="382.1437a"/>
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</size>
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<size W="1.71" L="1">
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<leakage_current subthreshold="160.8168p" gate="1.6835p"/>
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<capacitance C_g="343.4600a" C_s="399.1950a" C_d="399.4459a"/>
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</size>
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<size W="1.80" L="1">
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<leakage_current subthreshold="168.8585p" gate="1.7815p"/>
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<capacitance C_g="361.5356a" C_s="418.6455a" C_d="418.9109a"/>
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</size>
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<size W="1.89" L="1">
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<leakage_current subthreshold="176.9891p" gate="1.8797p"/>
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<capacitance C_g="379.6113a" C_s="438.0960a" C_d="438.3760a"/>
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</size>
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<size W="1.98" L="1">
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<leakage_current subthreshold="185.1987p" gate="1.9783p"/>
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<capacitance C_g="397.6872a" C_s="457.5465a" C_d="457.8412a"/>
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</size>
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<size W="2.08" L="1">
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<leakage_current subthreshold="194.4031p" gate="2.0881p"/>
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<capacitance C_g="417.7717a" C_s="479.1582a" C_d="479.4692a"/>
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</size>
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<size W="2.18" L="1">
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<leakage_current subthreshold="203.6850p" gate="2.1981p"/>
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<capacitance C_g="437.8563a" C_s="500.7698a" C_d="501.0973a"/>
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</size>
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<size W="2.29" L="1">
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<leakage_current subthreshold="213.9750p" gate="2.3194p"/>
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<capacitance C_g="459.9496a" C_s="524.5426a" C_d="524.8882a"/>
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</size>
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<size W="2.41" L="1">
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<leakage_current subthreshold="225.2852p" gate="2.4519p"/>
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<capacitance C_g="484.0515a" C_s="550.4765a" C_d="550.8420a"/>
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</size>
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<size W="2.53" L="1">
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<leakage_current subthreshold="236.6741p" gate="2.5848p"/>
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</size>
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<size W="2.65" L="1">
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<leakage_current subthreshold="248.1331p" gate="2.7179p"/>
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<capacitance C_g="532.2557a" C_s="602.3444a" C_d="602.7497a"/>
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</size>
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<size W="2.79" L="1">
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<leakage_current subthreshold="261.5809p" gate="2.8734p"/>
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<capacitance C_g="560.3751a" C_s="632.6007a" C_d="633.0293a"/>
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</size>
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<size W="2.93" L="1">
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<leakage_current subthreshold="275.1044p" gate="3.0292p"/>
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<capacitance C_g="588.4946a" C_s="662.8569a" C_d="663.3090a"/>
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</size>
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<size W="3.07" L="1">
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<leakage_current subthreshold="288.6954p" gate="3.1852p"/>
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<capacitance C_g="616.6143a" C_s="693.1131a" C_d="693.5887a"/>
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</size>
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<size W="3.23" L="1">
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<leakage_current subthreshold="304.3017p" gate="3.3637p"/>
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<capacitance C_g="648.7512a" C_s="727.6916a" C_d="728.1941a"/>
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</size>
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<size W="3.39" L="1">
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<leakage_current subthreshold="319.9781p" gate="3.5424p"/>
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<capacitance C_g="680.8882a" C_s="762.2702a" C_d="762.7996a"/>
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</size>
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<size W="3.56" L="1">
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<leakage_current subthreshold="336.7027p" gate="3.7325p"/>
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<capacitance C_g="715.0338a" C_s="799.0098a" C_d="799.5680a"/>
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</size>
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<size W="3.73" L="1">
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<leakage_current subthreshold="353.4904p" gate="3.9228p"/>
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<capacitance C_g="749.1796a" C_s="835.7495a" C_d="836.3364a"/>
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</size>
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<size W="3.92" L="1">
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<leakage_current subthreshold="372.3198p" gate="4.1358p"/>
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<capacitance C_g="787.3427a" C_s="876.8114a" C_d="877.4305a"/>
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<size W="4.12" L="1">
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<leakage_current subthreshold="392.2083p" gate="4.3601p"/>
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<capacitance C_g="827.5145a" C_s="920.0346a" C_d="920.6875a"/>
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<size transistor_size="3.05" power=""/>
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<size transistor_size="3.81" power=""/>
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<size transistor_size="4.77" power=""/>
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<size transistor_size="5.96" power=""/>
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<size transistor_size="7.45" power=""/>
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<size transistor_size="9.31" power=""/>
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<size transistor_size="11.64" power=""/>
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<size transistor_size="14.55" power=""/>
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<size transistor_size="18.19" power=""/>
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<size transistor_size="22.74" power=""/>
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</inputs>
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</mux>
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|
<lut>
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|
<inputs num_inputs="2">
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|
<size transistor_size="1.00" power=""/>
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<size transistor_size="1.25" power=""/>
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<size transistor_size="1.56" power=""/>
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<size transistor_size="1.95" power=""/>
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<size transistor_size="2.44" power=""/>
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<size transistor_size="3.05" power=""/>
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<size transistor_size="3.81" power=""/>
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<size transistor_size="4.77" power=""/>
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<size transistor_size="5.96" power=""/>
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<size transistor_size="7.45" power=""/>
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<size transistor_size="9.31" power=""/>
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<size transistor_size="11.64" power=""/>
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<size transistor_size="14.55" power=""/>
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<size transistor_size="18.19" power=""/>
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<size transistor_size="22.74" power=""/>
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</inputs>
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<inputs num_inputs="4">
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|
<size transistor_size="1.00" power=""/>
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<size transistor_size="1.25" power=""/>
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<size transistor_size="1.56" power=""/>
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<size transistor_size="1.95" power=""/>
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<size transistor_size="2.44" power=""/>
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<size transistor_size="3.05" power=""/>
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<size transistor_size="3.81" power=""/>
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<size transistor_size="4.77" power=""/>
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<size transistor_size="5.96" power=""/>
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<size transistor_size="7.45" power=""/>
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<size transistor_size="9.31" power=""/>
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<size transistor_size="11.64" power=""/>
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<size transistor_size="14.55" power=""/>
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<size transistor_size="18.19" power=""/>
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<size transistor_size="22.74" power=""/>
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</inputs>
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|
<inputs num_inputs="6">
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|
<size transistor_size="1.00" power=""/>
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|
<size transistor_size="1.25" power=""/>
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|
<size transistor_size="1.56" power=""/>
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<size transistor_size="1.95" power=""/>
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<size transistor_size="2.44" power=""/>
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<size transistor_size="3.05" power=""/>
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<size transistor_size="3.81" power=""/>
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<size transistor_size="4.77" power=""/>
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<size transistor_size="5.96" power=""/>
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<size transistor_size="7.45" power=""/>
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<size transistor_size="9.31" power=""/>
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<size transistor_size="11.64" power=""/>
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<size transistor_size="14.55" power=""/>
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<size transistor_size="18.19" power=""/>
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|
<size transistor_size="22.74" power=""/>
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|
</inputs>
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|
</lut>
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|
<dff>
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|
<inputs num_inputs="1">
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|
<size transistor_size="1" power=""/>
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<size transistor_size="2" power=""/>
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<size transistor_size="4" power=""/>
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<size transistor_size="8" power=""/>
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</inputs>
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</dff>
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</components>
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</technology>
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