riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/openfpga_flow/tasks/basic_tests/preconfig_testbench
History
tangxifan 919d6d8608 [test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches 2023-06-25 22:49:51 -07:00
..
configuration_chain/config Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00
configuration_chain_config_done_io/config [Test] Update test case by using GPIO with config_done signals 2022-02-24 09:49:34 -08:00
configuration_chain_no_time_stamp/config [Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp 2022-01-25 16:41:36 -08:00
configuration_frame/config Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00
flatten_memory/config Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00
fpga_core_wrapper/config [test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches 2023-06-25 22:49:51 -07:00
fpga_core_wrapper_naming_rules/config [test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches 2023-06-25 22:49:51 -07:00
fpga_core_wrapper_naming_rules_use_core_tb/config [test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches 2023-06-25 22:49:51 -07:00
memory_bank/config Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00
preconfigured_testbench_without_self_checking/config Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00