324 lines
12 KiB
C++
324 lines
12 KiB
C++
/********************************************************************
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* This function includes the module builders for essential logic gates
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* which are the leaf circuit model in the circuit library
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "build_essential_modules.h"
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#include "module_manager_utils.h"
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#include "openfpga_naming.h"
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "vtr_time.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/************************************************
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* Build a module of inverter or buffer
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* or tapered buffer to a file
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***********************************************/
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static void build_invbuf_module(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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/* Find the input port, output port and global inputs*/
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std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(
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circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
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std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(
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circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
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std::vector<CircuitPortId> global_ports =
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circuit_lib.model_global_ports_by_type(
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circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
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/* Make sure:
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* There is only 1 input port and 1 output port,
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* each size of which is 1
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*/
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VTR_ASSERT((1 == input_ports.size()) &&
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(1 == circuit_lib.port_size(input_ports[0])));
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VTR_ASSERT((1 == output_ports.size()) &&
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(1 == circuit_lib.port_size(output_ports[0])));
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/* TODO: move the check codes to check_circuit_library.h */
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/* If the circuit model is power-gated, we need to find at least one global
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* config_enable signals */
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if (true == circuit_lib.is_power_gated(circuit_model)) {
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/* Check all the ports we have are good for a power-gated circuit model */
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size_t num_err = 0;
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/* We need at least one global port */
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if (0 == global_ports.size()) {
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num_err++;
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}
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/* All the global ports should be config_enable */
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for (const auto& port : global_ports) {
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if (false == circuit_lib.port_is_config_enable(port)) {
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num_err++;
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}
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}
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/* Report errors if there are any */
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if (0 < num_err) {
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Inverter/buffer circuit model '%s' is power-gated. At "
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"least one config-enable global port is required!\n",
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circuit_lib.model_name(circuit_model).c_str());
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exit(1);
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}
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}
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/* Create a Verilog Module based on the circuit model, and add to module
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* manager */
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ModuleId module_id = add_circuit_model_to_module_manager(
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module_manager, circuit_lib, circuit_model);
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VTR_ASSERT(true == module_manager.valid_module_id(module_id));
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}
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/************************************************
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* Build a module of a pass-gate,
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* either transmission-gate or pass-transistor
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***********************************************/
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static void build_passgate_module(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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/* Find the input port, output port*/
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std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(
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circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
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std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(
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circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
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std::vector<CircuitPortId> global_ports =
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circuit_lib.model_global_ports_by_type(
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circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
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switch (circuit_lib.pass_gate_logic_type(circuit_model)) {
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case CIRCUIT_MODEL_PASS_GATE_TRANSMISSION:
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/* Make sure:
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* There is only 3 input port (in, sel, selb),
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* each size of which is 1
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*/
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VTR_ASSERT(3 == input_ports.size());
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for (const auto& input_port : input_ports) {
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VTR_ASSERT(1 == circuit_lib.port_size(input_port));
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}
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break;
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case CIRCUIT_MODEL_PASS_GATE_TRANSISTOR:
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/* Make sure:
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* There is only 2 input port (in, sel),
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* each size of which is 1
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*/
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VTR_ASSERT(2 == input_ports.size());
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for (const auto& input_port : input_ports) {
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VTR_ASSERT(1 == circuit_lib.port_size(input_port));
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}
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break;
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid topology for circuit model '%s'!\n",
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circuit_lib.model_name(circuit_model).c_str());
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exit(1);
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}
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/* Make sure:
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* There is only 1 output port,
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* each size of which is 1
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*/
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VTR_ASSERT((1 == output_ports.size()) &&
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(1 == circuit_lib.port_size(output_ports[0])));
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/* Create a Verilog Module based on the circuit model, and add to module
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* manager */
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ModuleId module_id = add_circuit_model_to_module_manager(
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module_manager, circuit_lib, circuit_model);
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VTR_ASSERT(true == module_manager.valid_module_id(module_id));
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}
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/************************************************
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* Build a module of a logic gate
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* which are standard cells
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* Supported gate types:
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* 1. N-input AND
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* 2. N-input OR
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* 3. 2-input MUX
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***********************************************/
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static void build_gate_module(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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/* Find the input port, output port*/
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std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(
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circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
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std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(
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circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
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std::vector<CircuitPortId> global_ports =
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circuit_lib.model_global_ports_by_type(
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circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
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/* Make sure:
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* There is only 1 output port,
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* each size of which is 1
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*/
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VTR_ASSERT((1 == output_ports.size()) &&
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(1 == circuit_lib.port_size(output_ports[0])));
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/* Create a Verilog Module based on the circuit model, and add to module
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* manager */
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ModuleId module_id = add_circuit_model_to_module_manager(
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module_manager, circuit_lib, circuit_model);
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VTR_ASSERT(true == module_manager.valid_module_id(module_id));
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}
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/************************************************
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* Generate the modules for essential gates
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* include inverters, buffers, transmission-gates,
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* etc.
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***********************************************/
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void build_essential_modules(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib) {
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vtr::ScopedStartFinishTimer timer(
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"Build essential (inverter/buffer/logic gate) modules");
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for (const auto& circuit_model : circuit_lib.models()) {
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/* Add essential modules upon on demand: only when it is not yet in the
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* module library */
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ModuleId module =
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module_manager.find_module(circuit_lib.model_name(circuit_model));
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if (true == module_manager.valid_module_id(module)) {
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continue;
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}
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if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) {
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build_invbuf_module(module_manager, circuit_lib, circuit_model);
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continue;
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}
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if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) {
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build_passgate_module(module_manager, circuit_lib, circuit_model);
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continue;
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}
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if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_model)) {
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build_gate_module(module_manager, circuit_lib, circuit_model);
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continue;
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}
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}
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}
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/*********************************************************************
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* Register all the user-defined modules in the module manager
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* Walk through the circuit library and add user-defined circuit models
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* to the module_manager
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********************************************************************/
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void build_user_defined_modules(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib) {
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vtr::ScopedStartFinishTimer timer("Build user-defined modules");
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/* Iterate over Verilog modules */
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for (const auto& model : circuit_lib.models()) {
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/* We only care about user-defined models */
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if ((true == circuit_lib.model_verilog_netlist(model).empty()) &&
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(true == circuit_lib.model_spice_netlist(model).empty())) {
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continue;
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}
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/* Skip Routing channel wire models because they need a different name. Do
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* it later */
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if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {
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continue;
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}
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/* Reach here, the model requires a user-defined Verilog netlist,
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* Register it in the module_manager
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*/
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add_circuit_model_to_module_manager(module_manager, circuit_lib, model);
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}
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}
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/*********************************************************************
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* This function will build a constant generator modules
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* and add it to the module manager
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* It could be either
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* 1. VDD or 2. GND
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* Each module will have only one output port
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********************************************************************/
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static void build_constant_generator_module(ModuleManager& module_manager,
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const size_t& const_value) {
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ModuleId const_module =
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module_manager.add_module(generate_const_value_module_name(const_value));
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/* Add one output port */
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BasicPort const_output_port(
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generate_const_value_module_output_port_name(const_value), 1);
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module_manager.add_port(const_module, const_output_port,
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ModuleManager::MODULE_OUTPUT_PORT);
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/* Specify the usage of this module
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* 1: VDD
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* 0: GND
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*/
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if (1 == const_value) {
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module_manager.set_module_usage(const_module, ModuleManager::MODULE_VDD);
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} else {
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VTR_ASSERT(0 == const_value);
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module_manager.set_module_usage(const_module, ModuleManager::MODULE_VSS);
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}
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}
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/*********************************************************************
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* This function will add two constant generator modules
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* to the module manager
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* 1. VDD
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* 2. GND
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********************************************************************/
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void build_constant_generator_modules(ModuleManager& module_manager) {
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vtr::ScopedStartFinishTimer timer("Build constant generator modules");
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/* VDD */
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build_constant_generator_module(module_manager, 1);
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/* GND */
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build_constant_generator_module(module_manager, 0);
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}
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/*********************************************************************
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* This function will rename the ports of primitive modules
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* using lib_name instead of prefix
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* Primitive modules are defined as those modules in the module manager
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* which have user defined netlists
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********************************************************************/
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void rename_primitive_module_port_names(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib) {
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for (const CircuitModelId& model : circuit_lib.models()) {
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/* We only care about user-defined models */
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if ((true == circuit_lib.model_verilog_netlist(model).empty()) &&
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(true == circuit_lib.model_spice_netlist(model).empty())) {
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/* Exception circuit models as primitive cells
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* - Inverter, buffer, pass-gate logic, logic gate
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* which should be renamed even when auto-generated
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*/
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if ((CIRCUIT_MODEL_INVBUF != circuit_lib.model_type(model)) &&
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(CIRCUIT_MODEL_PASSGATE != circuit_lib.model_type(model)) &&
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(CIRCUIT_MODEL_GATE != circuit_lib.model_type(model))) {
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continue;
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}
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}
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/* Skip Routing channel wire models because they need a different name. Do
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* it later */
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if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {
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continue;
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}
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/* Find the module in module manager */
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ModuleId module = module_manager.find_module(circuit_lib.model_name(model));
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/* We must find one! */
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VTR_ASSERT(true == module_manager.valid_module_id(module));
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/* Rename all the ports to use lib_name! */
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for (const CircuitPortId& model_port : circuit_lib.model_ports(model)) {
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/* Find the module port in module manager. We used prefix when creating
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* the ports */
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ModulePortId module_port = module_manager.find_module_port(
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module, circuit_lib.port_prefix(model_port));
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/* We must find one! */
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VTR_ASSERT(true ==
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module_manager.valid_module_port_id(module, module_port));
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/* Name it with lib_name */
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module_manager.set_module_port_name(
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module, module_port, circuit_lib.port_lib_name(model_port));
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}
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}
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}
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} /* end namespace openfpga */
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