tangxifan 0f87ae9886 support switch block submodule Verilog generation by segments		2019-06-05 12:56:05 -06:00
..
base	support switch block submodule Verilog generation by segments	2019-06-05 12:56:05 -06:00
bitstream	updated bitstream to use new RRSwitchBlock as well as the report timing engine	2019-05-24 12:54:10 -06:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
router	support switch block submodule Verilog generation by segments	2019-06-05 12:56:05 -06:00
shell	Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb	2019-05-13 14:45:57 -06:00
spice	Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb	2019-05-13 14:45:57 -06:00
verilog	support switch block submodule Verilog generation by segments	2019-06-05 12:56:05 -06:00