636 lines
17 KiB
C++
636 lines
17 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/celltypes.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <set>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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using RTLIL::id2cstr;
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struct keep_cache_t
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{
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Design *design;
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dict<Module*, bool> cache;
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void reset(Design *design = nullptr)
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{
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this->design = design;
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cache.clear();
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}
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bool query(Module *module)
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{
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log_assert(design != nullptr);
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if (module == nullptr)
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return false;
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if (cache.count(module))
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return cache.at(module);
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cache[module] = true;
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if (!module->get_bool_attribute("\\keep")) {
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bool found_keep = false;
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for (auto cell : module->cells())
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if (query(cell)) found_keep = true;
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cache[module] = found_keep;
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}
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return cache[module];
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}
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bool query(Cell *cell)
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{
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if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$live", "$fair", "$cover", "$specify2", "$specify3", "$specrule"))
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return true;
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if (cell->has_keep_attr())
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return true;
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if (cell->module && cell->module->design)
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return query(cell->module->design->module(cell->type));
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return false;
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}
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};
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keep_cache_t keep_cache;
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CellTypes ct_reg, ct_all;
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int count_rm_cells, count_rm_wires;
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void rmunused_module_cells(Module *module, bool verbose)
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{
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SigMap sigmap(module);
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pool<Cell*> queue, unused;
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pool<SigBit> used_raw_bits;
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dict<SigBit, pool<Cell*>> wire2driver;
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dict<SigBit, vector<string>> driver_driver_logs;
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SigMap raw_sigmap;
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for (auto &it : module->connections_) {
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for (int i = 0; i < GetSize(it.second); i++) {
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if (it.second[i].wire != nullptr)
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raw_sigmap.add(it.first[i], it.second[i]);
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}
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}
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for (auto &it : module->cells_) {
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Cell *cell = it.second;
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for (auto &it2 : cell->connections()) {
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if (ct_all.cell_known(cell->type) && !ct_all.cell_output(cell->type, it2.first))
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continue;
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for (auto raw_bit : it2.second) {
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if (raw_bit.wire == nullptr)
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continue;
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auto bit = sigmap(raw_bit);
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if (bit.wire == nullptr && ct_all.cell_known(cell->type))
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driver_driver_logs[raw_sigmap(raw_bit)].push_back(stringf("Driver-driver conflict "
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"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
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log_signal(raw_bit), log_id(cell), log_id(it2.first), log_signal(bit), log_id(module)));
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if (bit.wire != nullptr)
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wire2driver[bit].insert(cell);
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}
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}
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if (keep_cache.query(cell))
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queue.insert(cell);
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else
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unused.insert(cell);
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}
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for (auto &it : module->wires_) {
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Wire *wire = it.second;
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if (wire->port_output || wire->get_bool_attribute("\\keep")) {
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for (auto bit : sigmap(wire))
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for (auto c : wire2driver[bit])
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queue.insert(c), unused.erase(c);
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for (auto raw_bit : SigSpec(wire))
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used_raw_bits.insert(raw_sigmap(raw_bit));
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}
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}
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while (!queue.empty())
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{
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pool<SigBit> bits;
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for (auto cell : queue)
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for (auto &it : cell->connections())
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if (!ct_all.cell_known(cell->type) || ct_all.cell_input(cell->type, it.first))
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for (auto bit : sigmap(it.second))
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bits.insert(bit);
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queue.clear();
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for (auto bit : bits)
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for (auto c : wire2driver[bit])
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if (unused.count(c))
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queue.insert(c), unused.erase(c);
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}
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unused.sort(RTLIL::sort_by_name_id<RTLIL::Cell>());
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for (auto cell : unused) {
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if (verbose)
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log_debug(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str());
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module->design->scratchpad_set_bool("opt.did_something", true);
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module->remove(cell);
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count_rm_cells++;
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}
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for (auto &it : module->cells_) {
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Cell *cell = it.second;
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for (auto &it2 : cell->connections()) {
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if (ct_all.cell_known(cell->type) && !ct_all.cell_input(cell->type, it2.first))
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continue;
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for (auto raw_bit : raw_sigmap(it2.second))
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used_raw_bits.insert(raw_bit);
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}
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}
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for (auto it : driver_driver_logs) {
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if (used_raw_bits.count(it.first))
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for (auto msg : it.second)
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log_warning("%s\n", msg.c_str());
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}
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}
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int count_nontrivial_wire_attrs(RTLIL::Wire *w)
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{
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int count = w->attributes.size();
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count -= w->attributes.count("\\src");
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count -= w->attributes.count("\\unused_bits");
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return count;
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}
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bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPool &conns, pool<RTLIL::Wire*> &direct_wires)
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{
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RTLIL::Wire *w1 = s1.wire;
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RTLIL::Wire *w2 = s2.wire;
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if (w1 == NULL || w2 == NULL)
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return w2 == NULL;
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if (w1->port_input != w2->port_input)
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return w2->port_input;
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if ((w1->port_input && w1->port_output) != (w2->port_input && w2->port_output))
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return !(w2->port_input && w2->port_output);
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if (w1->name[0] == '\\' && w2->name[0] == '\\') {
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if (regs.check_any(s1) != regs.check_any(s2))
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return regs.check_any(s2);
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if (direct_wires.count(w1) != direct_wires.count(w2))
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return direct_wires.count(w2) != 0;
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if (conns.check_any(s1) != conns.check_any(s2))
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return conns.check_any(s2);
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}
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if (w1->port_output != w2->port_output)
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return w2->port_output;
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if (w1->name[0] != w2->name[0])
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return w2->name[0] == '\\';
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int attrs1 = count_nontrivial_wire_attrs(w1);
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int attrs2 = count_nontrivial_wire_attrs(w2);
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if (attrs1 != attrs2)
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return attrs2 > attrs1;
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return strcmp(w2->name.c_str(), w1->name.c_str()) < 0;
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}
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bool check_public_name(RTLIL::IdString id)
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{
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const std::string &id_str = id.str();
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if (id_str[0] == '$')
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return false;
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if (id_str.substr(0, 2) == "\\_" && (id_str[id_str.size()-1] == '_' || id_str.find("_[") != std::string::npos))
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return false;
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if (id_str.find(".$") != std::string::npos)
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return false;
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return true;
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}
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bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose)
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{
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SigPool register_signals;
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SigPool connected_signals;
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if (!purge_mode)
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for (auto &it : module->cells_) {
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RTLIL::Cell *cell = it.second;
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if (ct_reg.cell_known(cell->type))
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for (auto &it2 : cell->connections())
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if (ct_reg.cell_output(cell->type, it2.first))
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register_signals.add(it2.second);
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for (auto &it2 : cell->connections())
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connected_signals.add(it2.second);
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}
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SigMap assign_map(module);
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pool<RTLIL::SigSpec> direct_sigs;
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pool<RTLIL::Wire*> direct_wires;
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for (auto &it : module->cells_) {
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RTLIL::Cell *cell = it.second;
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if (ct_all.cell_known(cell->type))
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for (auto &it2 : cell->connections())
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if (ct_all.cell_output(cell->type, it2.first))
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direct_sigs.insert(assign_map(it2.second));
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}
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for (auto &it : module->wires_) {
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if (direct_sigs.count(assign_map(it.second)) || it.second->port_input)
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direct_wires.insert(it.second);
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}
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for (auto &it : module->wires_) {
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RTLIL::Wire *wire = it.second;
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for (int i = 0; i < wire->width; i++) {
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RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1);
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if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires))
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assign_map.add(s1);
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}
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}
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module->connections_.clear();
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SigPool used_signals;
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SigPool raw_used_signals;
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SigPool used_signals_nodrivers;
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for (auto &it : module->cells_) {
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RTLIL::Cell *cell = it.second;
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for (auto &it2 : cell->connections_) {
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assign_map.apply(it2.second);
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raw_used_signals.add(it2.second);
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used_signals.add(it2.second);
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if (!ct_all.cell_output(cell->type, it2.first))
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used_signals_nodrivers.add(it2.second);
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}
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}
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for (auto &it : module->wires_) {
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RTLIL::Wire *wire = it.second;
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if (wire->port_id > 0) {
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RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
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raw_used_signals.add(sig);
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assign_map.apply(sig);
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used_signals.add(sig);
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if (!wire->port_input)
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used_signals_nodrivers.add(sig);
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}
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if (wire->get_bool_attribute("\\keep")) {
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RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
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assign_map.apply(sig);
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used_signals.add(sig);
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}
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}
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pool<RTLIL::Wire*> del_wires_queue;
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for (auto wire : module->wires())
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{
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SigSpec s1 = SigSpec(wire), s2 = assign_map(s1);
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log_assert(GetSize(s1) == GetSize(s2));
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Const initval;
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if (wire->attributes.count("\\init"))
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initval = wire->attributes.at("\\init");
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if (GetSize(initval) != GetSize(wire))
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initval.bits.resize(GetSize(wire), State::Sx);
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if (initval.is_fully_undef())
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wire->attributes.erase("\\init");
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if (GetSize(wire) == 0) {
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// delete zero-width wires, unless they are module ports
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if (wire->port_id == 0)
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goto delete_this_wire;
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} else
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if (wire->port_id != 0 || wire->get_bool_attribute("\\keep") || !initval.is_fully_undef()) {
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// do not delete anything with "keep" or module ports or initialized wires
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} else
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if (!purge_mode && check_public_name(wire->name) && (raw_used_signals.check_any(s1) || used_signals.check_any(s2) || s1 != s2)) {
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// do not get rid of public names unless in purge mode or if the wire is entirely unused, not even aliased
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} else
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if (!raw_used_signals.check_any(s1)) {
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// delete wires that aren't used by anything directly
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goto delete_this_wire;
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} else
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if (!used_signals.check_any(s2)) {
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// delete wires that aren't used by anything indirectly, even though other wires may alias it
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goto delete_this_wire;
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}
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if (0)
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{
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delete_this_wire:
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del_wires_queue.insert(wire);
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}
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else
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{
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RTLIL::SigSig new_conn;
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for (int i = 0; i < GetSize(s1); i++)
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if (s1[i] != s2[i]) {
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if (s2[i] == State::Sx && (initval[i] == State::S0 || initval[i] == State::S1)) {
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s2[i] = initval[i];
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initval[i] = State::Sx;
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}
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new_conn.first.append_bit(s1[i]);
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new_conn.second.append_bit(s2[i]);
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}
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if (new_conn.first.size() > 0) {
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if (initval.is_fully_undef())
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wire->attributes.erase("\\init");
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else
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wire->attributes.at("\\init") = initval;
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used_signals.add(new_conn.first);
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used_signals.add(new_conn.second);
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module->connect(new_conn);
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}
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if (!used_signals_nodrivers.check_all(s2)) {
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std::string unused_bits;
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for (int i = 0; i < GetSize(s2); i++) {
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if (s2[i].wire == NULL)
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continue;
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if (!used_signals_nodrivers.check(s2[i])) {
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if (!unused_bits.empty())
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unused_bits += " ";
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unused_bits += stringf("%d", i);
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}
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}
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if (unused_bits.empty() || wire->port_id != 0)
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wire->attributes.erase("\\unused_bits");
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else
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wire->attributes["\\unused_bits"] = RTLIL::Const(unused_bits);
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} else {
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wire->attributes.erase("\\unused_bits");
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}
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}
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}
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int del_temp_wires_count = 0;
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for (auto wire : del_wires_queue) {
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if (ys_debug() || (check_public_name(wire->name) && verbose))
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log_debug(" removing unused non-port wire %s.\n", wire->name.c_str());
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else
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del_temp_wires_count++;
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}
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module->remove(del_wires_queue);
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count_rm_wires += GetSize(del_wires_queue);
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if (verbose && del_temp_wires_count)
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log_debug(" removed %d unused temporary wires.\n", del_temp_wires_count);
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return !del_wires_queue.empty();
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}
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bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose)
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{
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bool did_something = false;
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CellTypes fftypes;
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fftypes.setup_internals_mem();
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SigMap sigmap(module);
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dict<SigBit, State> qbits;
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for (auto cell : module->cells())
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if (fftypes.cell_known(cell->type) && cell->hasPort("\\Q"))
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{
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SigSpec sig = cell->getPort("\\Q");
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for (int i = 0; i < GetSize(sig); i++)
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{
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SigBit bit = sig[i];
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if (bit.wire == nullptr || bit.wire->attributes.count("\\init") == 0)
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continue;
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Const init = bit.wire->attributes.at("\\init");
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if (i >= GetSize(init) || init[i] == State::Sx || init[i] == State::Sz)
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continue;
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sigmap.add(bit);
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qbits[bit] = init[i];
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}
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}
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for (auto wire : module->wires())
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{
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if (!purge_mode && wire->name[0] == '\\')
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continue;
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if (wire->attributes.count("\\init") == 0)
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continue;
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Const init = wire->attributes.at("\\init");
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for (int i = 0; i < GetSize(wire) && i < GetSize(init); i++)
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{
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if (init[i] == State::Sx || init[i] == State::Sz)
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continue;
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SigBit wire_bit = SigBit(wire, i);
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SigBit mapped_wire_bit = sigmap(wire_bit);
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if (wire_bit == mapped_wire_bit)
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goto next_wire;
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if (qbits.count(sigmap(SigBit(wire, i))) == 0)
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goto next_wire;
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if (qbits.at(sigmap(SigBit(wire, i))) != init[i])
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goto next_wire;
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}
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if (verbose)
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log_debug(" removing redundant init attribute on %s.\n", log_id(wire));
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wire->attributes.erase("\\init");
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did_something = true;
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next_wire:;
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}
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return did_something;
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}
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void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool rminit)
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{
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if (verbose)
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log("Finding unused cells or wires in module %s..\n", module->name.c_str());
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std::vector<RTLIL::Cell*> delcells;
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for (auto cell : module->cells())
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if (cell->type.in("$pos", "$_BUF_") && !cell->has_keep_attr()) {
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bool is_signed = cell->type == "$pos" && cell->getParam("\\A_SIGNED").as_bool();
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RTLIL::SigSpec a = cell->getPort("\\A");
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RTLIL::SigSpec y = cell->getPort("\\Y");
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a.extend_u0(GetSize(y), is_signed);
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module->connect(y, a);
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delcells.push_back(cell);
|
|
}
|
|
for (auto cell : delcells) {
|
|
if (verbose)
|
|
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name.c_str(),
|
|
log_signal(cell->getPort("\\Y")), log_signal(cell->getPort("\\A")));
|
|
module->remove(cell);
|
|
}
|
|
if (!delcells.empty())
|
|
module->design->scratchpad_set_bool("opt.did_something", true);
|
|
|
|
rmunused_module_cells(module, verbose);
|
|
while (rmunused_module_signals(module, purge_mode, verbose)) { }
|
|
|
|
if (rminit && rmunused_module_init(module, purge_mode, verbose))
|
|
while (rmunused_module_signals(module, purge_mode, verbose)) { }
|
|
}
|
|
|
|
struct OptCleanPass : public Pass {
|
|
OptCleanPass() : Pass("opt_clean", "remove unused cells and wires") { }
|
|
void help() YS_OVERRIDE
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" opt_clean [options] [selection]\n");
|
|
log("\n");
|
|
log("This pass identifies wires and cells that are unused and removes them. Other\n");
|
|
log("passes often remove cells but leave the wires in the design or reconnect the\n");
|
|
log("wires but leave the old cells in the design. This pass can be used to clean up\n");
|
|
log("after the passes that do the actual work.\n");
|
|
log("\n");
|
|
log("This pass only operates on completely selected modules without processes.\n");
|
|
log("\n");
|
|
log(" -purge\n");
|
|
log(" also remove internal nets if they have a public name\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
|
{
|
|
bool purge_mode = false;
|
|
|
|
log_header(design, "Executing OPT_CLEAN pass (remove unused cells and wires).\n");
|
|
log_push();
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
if (args[argidx] == "-purge") {
|
|
purge_mode = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
keep_cache.reset(design);
|
|
|
|
ct_reg.setup_internals_mem();
|
|
ct_reg.setup_stdcells_mem();
|
|
|
|
ct_all.setup(design);
|
|
|
|
count_rm_cells = 0;
|
|
count_rm_wires = 0;
|
|
|
|
for (auto module : design->selected_whole_modules_warn()) {
|
|
if (module->has_processes_warn())
|
|
continue;
|
|
rmunused_module(module, purge_mode, true, true);
|
|
}
|
|
|
|
if (count_rm_cells > 0 || count_rm_wires > 0)
|
|
log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
|
|
|
|
design->optimize();
|
|
design->sort();
|
|
design->check();
|
|
|
|
keep_cache.reset();
|
|
ct_reg.clear();
|
|
ct_all.clear();
|
|
log_pop();
|
|
}
|
|
} OptCleanPass;
|
|
|
|
struct CleanPass : public Pass {
|
|
CleanPass() : Pass("clean", "remove unused cells and wires") { }
|
|
void help() YS_OVERRIDE
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" clean [options] [selection]\n");
|
|
log("\n");
|
|
log("This is identical to 'opt_clean', but less verbose.\n");
|
|
log("\n");
|
|
log("When commands are separated using the ';;' token, this command will be executed\n");
|
|
log("between the commands.\n");
|
|
log("\n");
|
|
log("When commands are separated using the ';;;' token, this command will be executed\n");
|
|
log("in -purge mode between the commands.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
|
{
|
|
bool purge_mode = false;
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
if (args[argidx] == "-purge") {
|
|
purge_mode = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
if (argidx < args.size())
|
|
extra_args(args, argidx, design);
|
|
|
|
keep_cache.reset(design);
|
|
|
|
ct_reg.setup_internals_mem();
|
|
ct_reg.setup_stdcells_mem();
|
|
|
|
ct_all.setup(design);
|
|
|
|
count_rm_cells = 0;
|
|
count_rm_wires = 0;
|
|
|
|
for (auto module : design->selected_whole_modules()) {
|
|
if (module->has_processes())
|
|
continue;
|
|
rmunused_module(module, purge_mode, ys_debug(), false);
|
|
}
|
|
|
|
log_suppressed();
|
|
if (count_rm_cells > 0 || count_rm_wires > 0)
|
|
log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
|
|
|
|
design->optimize();
|
|
design->sort();
|
|
design->check();
|
|
|
|
keep_cache.reset();
|
|
ct_reg.clear();
|
|
ct_all.clear();
|
|
}
|
|
} CleanPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|