44 lines
1.7 KiB
Plaintext
44 lines
1.7 KiB
Plaintext
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=vpr_blif
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif
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[SYNTHESIS_PARAM]
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bench0_top = pipelined_8bit_adder
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bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.act
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bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v
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bench0_chan_width = 100
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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min_route_chan_width=1.3
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vpr_fpga_verilog_include_icarus_simulator=
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vpr_fpga_verilog_formal_verification_top_netlist=
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vpr_fpga_verilog_include_timing=
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vpr_fpga_verilog_include_signal_init=
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vpr_fpga_verilog_print_autocheck_top_testbench=
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vpr_fpga_bitstream_generator=
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#vpr_fpga_verilog_print_user_defined_template=
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#vpr_fpga_verilog_print_report_timing_tcl=
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#vpr_fpga_verilog_print_sdc_pnr=
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#vpr_fpga_verilog_print_sdc_analysis=
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vpr_fpga_verilog_explicit_mapping=
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vpr_fpga_x2p_compact_routing_hierarchy=
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end_flow_with_test=
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