75 lines
3.1 KiB
Plaintext
75 lines
3.1 KiB
Plaintext
# Standard Configuration Example
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[CAD_TOOLS_PATH]
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openfpga_shell_path = ${PATH:OPENFPGA_PATH}/build/openfpga/openfpga
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yosys_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys
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misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc
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odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe
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abc_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys-abc
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abc_mccl_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc
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abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/abc/abc
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vpr_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/vpr/vpr
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ace_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/ace2/ace
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pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl
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iverilog_path = iverilog
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include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr/VerilogNetlists
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[FLOW_SCRIPT_CONFIG]
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valid_flows = vpr_blif,yosys_vpr
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[DEFAULT_PARSE_RESULT_VPR]
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# parser format <name of variable> = <regex string>, <lambda function/type>
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clb_blocks = "Netlist clb blocks: ([0-9]+)", str
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io_blocks = "Netlist io blocks: ([0-9]+)", str
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mult_blocks = "Netlist mult_36 blocks: ([0-9]+)", str
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memory_blocks = "Netlist memory blocks: ([0-9]+)", str
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logic_delay = "Total logic delay: ([0-9.]+)", str
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total_net_delay = "total net delay: ([0-9.]+)", str
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total_routing_area = "Total routing area: ([0-9.]+[e|E\+[0-9]+)", str
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total_logic_block_area = "Total used logic block area: ([0-9.]+[e|E\+[0-9]+)", str
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total_wire_length = "Total wirelength: ([0-9]+)", str
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packing_time = "Packing took ([0-9.]+) seconds", str
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placement_time = "Placement took ([0-9.]+) seconds", str
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routing_time = "Routing took ([0-9.]+) seconds", str
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average_net_length = "average net length: ([0-9.]+)", str
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critical_path = "Final critical path: ([0-9.]+) ([a-z])s", scientific
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total_routing_time = "Routing took ([0-9.]+) seconds", float
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[DEFAULT_PARSE_RESULT_POWER]
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pb_type_power="PB Types\s+([0-9]+)", str
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routing_power="Routing\s+([0-9]+)", str
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switch_box_power="Switch Box\s+([0-9]+)", str
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connection_box_power="Connection Box\s+([0-9]+)", str
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primitives_power="Primitives\s+([0-9]+)", str
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interc_structures_power="Interc Structures\s+([0-9]+)", str
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lut6_power="^\s+lut6\s+([0-9]+)", str
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ff_power="^\s+ff\s+([0-9]+)", str
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[INTERMIDIATE_FILE_PREFIX]
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# Yosys files
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yosys_out_blif=${PATH:TOP_MODULE}_yosys_out.blif
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yosys_output=yosys_output.txt
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# ACE2 and intermidiate file
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activity_file=${PATH:TOP_MODULE}_ace_out.act
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ace_output_blif=${PATH:TOP_MODULE}_ace_out.blif
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corrected_format_blif=${PATH:TOP_MODULE}.blif
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blackbox_blif=${PATH:TOP_MODULE}_bb.blif
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# VPR Files
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min_chann_vpr_output=${PATH:TOP_MODULE}_min_chan_width_vpr.txt
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reroute_chan_vpr_output=${PATH:TOP_MODULE}_reroute_vpr.txt
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fixed_chan_vpr_output=${PATH:TOP_MODULE}_fr_chan_width.txt
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vpr_stat_parse_fn=vpr_stat.txt
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vpr_power_stat_parse_fn=vpr_power_stat.txt
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vpr_net_file=${PATH:TOP_MODULE}_vpr.net
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vpr_place_file=${PATH:TOP_MODULE}_vpr.place
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vpr_route_file=${PATH:TOP_MODULE}_vpr.route
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#Iverilog verification file
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iverilog_output=iverilog_output.txt
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vvp_output=vvp_sim_output.txt
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[CMD_ARGUMENT_DEPENDANCY]
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vpr_fpga_verilog=vpr_fpga_verilog_dir|abc
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vpr_fpga_verilog_dir=vpr_fpga_verilog
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