OpenFPGA/.gitmodules

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[submodule "yosys"]
path = yosys
url = https://github.com/YosysHQ/yosys
branch = release-branch-0.10
ignore = dirty
[submodule "yosys-plugins"]
path = yosys-plugins
url = https://github.com/SymbiFlow/yosys-symbiflow-plugins
[submodule "vtr-verilog-to-routing"]
path = vtr-verilog-to-routing
url = https://github.com/verilog-to-routing/vtr-verilog-to-routing.git
branch = openfpga