Go to file
tangxifan 0bc1659548
Merge pull request #1906 from lnis-uofu/xt_bitset
Support overwriting mode_bits for pb_type through bitstream setting file
2024-11-25 17:29:58 -08:00
.github [ci] now use download-artifact v4 2024-06-25 16:46:33 -07:00
cmake [script] remove the custom findTbb module for cmake as it is native in CMake 2024-05-06 15:42:54 -07:00
dev [script] debugging check format script 2022-10-06 19:13:13 -07:00
docker [docker] fix bugs on python3 2024-05-06 10:36:05 -07:00
docs [doc] add new syntax 2024-11-25 16:21:34 -08:00
libs [core] code format 2024-11-25 16:22:01 -08:00
openfpga [core] code format 2024-11-25 16:22:01 -08:00
openfpga_flow [test] add new test to validate default mode bit overwrite 2024-11-25 16:06:40 -08:00
vtr-verilog-to-routing@8178b71295 [lib] update vtr to latest 2024-11-13 10:44:25 -08:00
yosys@0200a7680a Bump yosys from `8893dad` to `0200a76` 2024-10-10 06:23:50 +00:00
yosys-plugins@dfe9b1a15b Bump yosys-plugins from `7c89a55` to `dfe9b1a` 2024-01-24 07:05:43 +00:00
.clang-format [ci] add C/C++ code format style file 2022-10-06 16:44:05 -07:00
.dockerignore [CiFix] Docker image 2022-08-29 00:40:37 -06:00
.gitignore [script] enable shared library for openfpga 2022-12-01 11:42:25 -08:00
.gitmodules [yosys] update to v0.22 2022-10-21 16:57:00 -07:00
.readthedocs.yml Update .readthedocs.yml 2024-08-03 00:26:24 -07:00
CMakeLists.txt Update build step to remove quicklogic-integrated-plugins-code, Update yosys to latest bump-version 2024-01-22 23:16:32 +05:30
Dockerfile Fixed binder dependecies 2023-07-16 21:54:30 -06:00
LICENSE Create LICENSE 2018-06-26 21:52:08 -07:00
Makefile [script] now use clang-format-14 as c++/c formatter 2024-05-05 16:16:43 -07:00
README.md [doc] format 2024-06-10 10:43:45 -07:00
VERSION.md Updated Patch Count 2024-11-14 05:34:04 +00:00
openfpga.sh [doc] format 2023-08-22 15:46:49 +08:00
requirements.txt [doc] update black version from 20.8b1 to 24.3.0 2024-04-10 12:57:31 -07:00

README.md

Getting Started with OpenFPGA

Test Cell Library Tests Code style: black Documentation Status Binder

Version: see VERSION.md

Introduction

The award-winning OpenFPGA framework is the first open-source FPGA IP generator with silicon proofs supporting highly-customizable FPGA architectures. OpenFPGA provides complete EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.

[!TIP] If this is your first time working with OpenFPGA, we strongly recommend you watch the introduction video about OpenFPGA

A quick overview of OpenFPGA tools can be found here. We also recommend potential users check out the summary of technical capabilities before compiling.

[!TIP] Before asking for help, please checkout the Frequently Asked Questions

Compilation

[!NOTE] A tutorial video about how to compile can be found here

Detailed guidelines are available at compilation guidelines. Before starting, we strongly recommend you read the required dependencies and ensure that they are correctly installed. It also includes detailed information about the docker image.

Documentation

OpenFPGA's full documentation includes tutorials, descriptions of the design flow, and tool options.

Tutorials

You can find a set of tutorials, with which you get familiar with the tool and use OpenFPGA for various purposes.

Backward Compatibility

If you were using an old version of OpenFPGA and are now interested to move to the latest version, please check out the developer guidelines.

License

All the codes are under MIT license, with the exception of submodules, e.g., VTR, Yosys and Yosys-plugin, which are distributed under its own (permissive) terms. See their full license for details.

How to Cite

Please use the following paper as a general citation for OpenFPGA:

X. Tang, E. Giacomin, B. Chauviere, A. Alacchi and P. -E. Gaillardon, "OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs," in IEEE Micro, vol. 40, no. 4, pp. 41-48, 1 July-Aug. 2020, doi: 10.1109/MM.2020.2995854.

Bibtex:

@ARTICLE{9098028,  author={Tang, Xifan and Giacomin, Edouard and Chauviere, Baudouin and Alacchi, Aurélien and Gaillardon, Pierre-Emmanuel},  journal={IEEE Micro},   title={OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs},   year={2020},  volume={40},  number={4},  pages={41-48},  doi={10.1109/MM.2020.2995854}}

A list of related publications can be found here.

Contributing to OpenFPGA

Please read the contributor guidelines if you would like to contribute to OpenFPGA.