27 lines
944 B
Plaintext
27 lines
944 B
Plaintext
- required time support
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- printing ABC version/platform in the output files
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- fix gcc compiler warnings
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- port "mfs" from MVSIS
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- improve AIG rewriting package
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- unify functional representation of local functions
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- additional rewriting options for delay optimization
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- experiment with yield-aware standard-cell mapping
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- improving area recovery in integrated sequential synthesis
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- high-effort logic synthesis for hard miters (cofactoring, Boolean division)
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- mapping into MV cells
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- SAT solver with linear constraints
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- specialized synthesis for EXORs and large MUXes
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- sequential AIG rewriting initial state computation
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- placement-aware mapping
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- sequential equivalence checking
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- parser for Verilog netlists
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- hierarchy manager (hierarchical BLIF/BLIF-MV parser)
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- required time based on all cuts
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- comparing tts of differently derived the same cut
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- area flow based AIG rewriting
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- cut frontier adjustment
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