156 lines
7.9 KiB
C
156 lines
7.9 KiB
C
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void init_list_include_verilog_netlists(t_spice* spice);
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void init_include_user_defined_verilog_netlists(t_spice spice);
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void dump_include_user_defined_verilog_netlists(FILE* fp,
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t_spice spice);
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void dump_verilog_file_header(FILE* fp,
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char* usage);
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FILE* verilog_create_one_subckt_file(char* subckt_dir,
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char* subckt_name_prefix,
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char* verilog_subckt_file_name_prefix,
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int grid_x, int grid_y,
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char** verilog_fname);
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void dump_verilog_subckt_header_file(t_llist* subckt_llist_head,
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char* subckt_dir,
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char* header_file_name);
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char determine_verilog_generic_port_split_sign(enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_generic_port(FILE* fp,
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enum e_dump_verilog_port_type dump_port_type,
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char* port_name, int port_lsb, int port_msb);
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void decode_verilog_memory_bank_sram(t_spice_model* cur_sram_spice_model, int sram_bit,
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int bl_len, int wl_len, int bl_offset, int wl_offset,
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int* bl_conf_bits, int* wl_conf_bits);
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void
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decode_and_add_verilog_sram_membank_conf_bit_to_llist(t_sram_orgz_info* cur_sram_orgz_info,
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int mem_index,
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int num_bl_per_sram, int num_wl_per_sram,
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int cur_sram_bit);
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void decode_verilog_one_level_4t1r_mux(int path_id,
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int bit_len, int* conf_bits);
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void decode_verilog_rram_mux(t_spice_model* mux_spice_model,
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int mux_size, int path_id,
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int* bit_len, int** conf_bits, int* mux_level);
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int determine_decoder_size(int num_addr_out);
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char* chomp_verilog_node_prefix(char* verilog_node_prefix);
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char* format_verilog_node_prefix(char* verilog_node_prefix);
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char* verilog_convert_port_type_to_string(enum e_spice_model_port_type port_type);
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int rec_dump_verilog_spice_model_global_ports(FILE* fp,
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t_spice_model* cur_spice_model,
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boolean dump_port_type,
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boolean recursive);
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int dump_verilog_global_ports(FILE* fp, t_llist* head,
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boolean dump_port_type);
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void dump_verilog_mux_sram_one_outport(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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t_spice_model* cur_mux_spice_model, int mux_size,
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int sram_lsb, int sram_msb,
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int port_type_index,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_sram_one_outport(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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int port_type_index,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_sram_outports(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_sram_one_port(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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int port_type_index,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_sram_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_reserved_sram_one_port(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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int port_type_index,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_reserved_sram_ports(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
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t_spice_model* cur_mux_verilog_model, int mux_size,
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t_spice_model* cur_sram_verilog_model);
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void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
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t_spice_model* sram_verilog_model);
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void dump_verilog_scff_config_bus(FILE* fp,
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t_spice_model* mem_spice_model,
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t_sram_orgz_info* cur_sram_orgz_info,
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int lsb, int msb,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_mem_config_bus(FILE* fp, t_spice_model* mem_spice_model,
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t_sram_orgz_info* cur_sram_orgz_info,
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int cur_num_sram,
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int num_mem_reserved_conf_bits,
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int num_mem_conf_bits);
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void dump_verilog_cmos_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model,
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t_sram_orgz_info* cur_sram_orgz_info,
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int mux_size, int cur_num_sram,
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int num_mux_reserved_conf_bits,
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int num_mux_conf_bits);
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void dump_verilog_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model,
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t_sram_orgz_info* cur_sram_orgz_info,
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int mux_size, int cur_num_sram,
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int num_mux_reserved_conf_bits,
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int num_mux_conf_bits);
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void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
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t_sram_orgz_info* cur_sram_orgz_info,
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int mux_size, int cur_num_sram,
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int num_mux_reserved_conf_bits,
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int num_mux_conf_bits);
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void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
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t_sram_orgz_info* cur_sram_orgz_info,
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int mux_size, int cur_num_sram,
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int num_mux_reserved_conf_bits,
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int num_mux_conf_bits);
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void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model,
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char* general_port_prefix, int lsb, int msb,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_sram_config_bus_internal_wires(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
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int lsb, int msb);
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void dump_verilog_toplevel_one_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type,
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int pin_index, int side,
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int x, int y,
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boolean dump_port_type);
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