111 lines
3.6 KiB
C
111 lines
3.6 KiB
C
/* Define global variables here */
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#include "vpr_types.h"
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#include "globals.h"
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/******** General global variables ********/
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int Fs_seed = -1;
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int W_seed = -1;
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int binary_search = -1;
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float grid_logic_tile_area = 0;
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float ipin_mux_trans_size = 0;
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/* User netlist information begin */
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int num_logical_nets = 0, num_logical_blocks = 0;
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int num_p_inputs = 0, num_p_outputs = 0;
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struct s_net *vpack_net = NULL;
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struct s_logical_block *logical_block = NULL;
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char *blif_circuit_name = NULL;
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char *default_output_name = NULL;
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/* User netlist information end */
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/******** Clustered netlist to be mapped stuff ********/
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int num_nets = 0;
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struct s_net *clb_net = NULL;
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int num_blocks = 0;
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struct s_block *block = NULL;
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int *clb_to_vpack_net_mapping = NULL; /* [0..num_clb_nets - 1] */
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int *vpack_to_clb_net_mapping = NULL; /* [0..num_vpack_nets - 1] */
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/* This identifies the t_type_ptr of an IO block */
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int num_types = 0;
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struct s_type_descriptor *type_descriptors = NULL;
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t_type_ptr IO_TYPE = NULL;
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t_type_ptr EMPTY_TYPE = NULL;
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t_type_ptr FILL_TYPE = NULL;
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/******** Physical architecture stuff ********/
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int nx = 0;
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int ny = 0;
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/* TRUE if this is a global clb pin -- an input pin to which the netlist can *
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* connect global signals, but which does not connect into the normal *
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* routing via muxes etc. Marking pins like this (only clocks in my work) *
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* stops them from screwing up the input switch pattern in the rr_graph *
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* generator and from creating extra switches that the area model would *
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* count. */
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int *chan_width_x = NULL; /* [0..ny] */
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int *chan_width_y = NULL; /* [0..nx] */
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struct s_grid_tile **grid = NULL; /* [0..(nx+1)][0..(ny+1)] Physical block list */
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/******** Structures defining the routing ********/
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/* Linked list start pointers. Define the routing. */
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struct s_trace **trace_head = NULL; /* [0..(num_nets-1)] */
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struct s_trace **trace_tail = NULL; /* [0..(num_nets-1)] */
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/******** Structures defining the FPGA routing architecture ********/
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int num_rr_nodes = 0;
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t_rr_node *rr_node = NULL; /* [0..(num_rr_nodes-1)] */
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t_ivec ***rr_node_indices = NULL;
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int num_rr_indexed_data = 0;
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t_rr_indexed_data *rr_indexed_data = NULL; /* [0..(num_rr_indexed_data-1)] */
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/* Gives the rr_node indices of net terminals. */
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int **net_rr_terminals = NULL; /* [0..num_nets-1][0..num_pins-1] */
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/* Gives information about all the switch types *
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* (part of routing architecture, but loaded in read_arch.c */
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struct s_switch_inf *switch_inf = NULL; /* [0..(det_routing_arch.num_switch-1)] */
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/* Stores the SOURCE and SINK nodes of all CLBs (not valid for pads). */
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int **rr_blk_source = NULL; /* [0..(num_blocks-1)][0..(num_class-1)] */
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/* primiary inputs removed from circuit */
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struct s_linked_vptr *circuit_p_io_removed = NULL;
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/********** Structures representing timing graph information */
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float pb_max_internal_delay = UNDEFINED; /* biggest internal delay of physical block */
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const t_pb_type *pbtype_max_internal_delay = NULL; /* physical block type with highest internal delay */
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/********** Structures representing the global clock network */
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t_clock_arch * g_clock_arch;
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/* Xifan TANG: FPGA-SPICE and Verilog Generator */
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/* Detailed routing information for each SB and CB */
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t_sb** sb_info = NULL;
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t_cb** cbx_info = NULL;
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t_cb** cby_info = NULL;
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/* Xifan TANG: detailed runtime statistics */
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float pack_route_time = 0.;
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/* Xifan TANG: clb_to_clb_directs*/
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int num_clb2clb_directs = 0;
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t_clb_to_clb_directs* clb2clb_direct = NULL;
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