tangxifan 86e7c963f8 [Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files		2021-10-02 22:19:20 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks	2021-07-02 17:28:17 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Test] Added a sample fabric key for 2-region QL memory bank	2021-09-22 11:25:16 -07:00
misc	[Script] Update yosys script using BRAMs	2021-04-27 21:44:27 -06:00
openfpga_arch	[Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files	2021-10-02 22:19:20 -07:00
openfpga_cell_library	[HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals	2021-10-01 17:06:35 -07:00
openfpga_shell_scripts	[Test] Bug fix	2021-06-29 18:51:28 -06:00
openfpga_simulation_settings	[Flow] Modify simulation setting example for QuickLogic memory bank using separated clks for BL and WL shift registers	2021-10-01 16:52:06 -07:00
openfpga_yosys_techlib	[Script] Add dff with active-low async reset to default yosys tech lib	2021-07-02 11:17:43 -06:00
regression_test_scripts	[Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests	2021-09-28 11:29:45 -07:00
scripts	Merge remote-tracking branch 'upstream/master'	2021-09-01 14:19:00 -07:00
tasks	[Flow] Add an example simulation setting file for defining programming shift register clocks	2021-10-01 11:04:23 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Patch architecture due to missing mode bit definition	2021-07-02 11:41:29 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00