139 lines
5.3 KiB
ReStructuredText
139 lines
5.3 KiB
ReStructuredText
.. _architecture_exploration:
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Architecture Exploration
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------------------------
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Architecture exploration is generally the first stage of any architecture design, and there are several ways to explore FPGA architectures.
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This tutorial will explain how to explore FPGA architecture using application benchmarking.
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This tutorial will detail how to evaluate the performance of different architectures for a given set of applications to understand which one is the most suitable.
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.. note:: We are not exploring the architecture of the application/design for FPGA implementation, but the architecture of the FPGA itself.
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Application Benchmarks
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^^^^^^^^^^^^^^^^^^^^^^
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The architecture exploration process starts with a set of applications that expects FPGA architecture customization.
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In the case of generic FPGA design, this benchmark suit may consist of applications from various domains.
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In this tutorial, we selected the following few designs from the `VTR benchmarks`.
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#. **ch_intrinsics** : Memory Init
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#. **diffeq1** : Arithematic Unit
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#. **diffeq2** : Arithematic Unit
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#. **sha** : Cryptography
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You will find these benchamrks in ``openfpga_flow/benchmarks/vtr_benchmark/`` directory.
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Candidate Architectures
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^^^^^^^^^^^^^^^^^^^^^^^
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The base candidate architectures are selected for evaluating the performance of the above applications and later iteratively analyzed and modified to improve overall performance. These base architectures are (in the case of OpenFPGA) modeled in an architecture XML file. The XML-based description enables the modeling of hundreds of different architectures in a human-readable format. In this tutorial, we will modify the `Flexible Logic Block` (FLE) of the FPGA to understand its impact on the application performance.
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The arch0 uses ten 6-input LUTs in each CLB, whereas the arch1 replaces the a fixed LUT-6 with fracturable LUT which can be operated in 1x LUT6 or 2x LUT5 mode.
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#. **arch0:** k6_N10_tileable.xml
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#. **arch1:** k6_frac_N10_tileable.xml
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Create OpenFPGA Task
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^^^^^^^^^^^^^^^^^^^^
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OpenFPGA works on the task-based structure, where you create a directory with a name of your choice, which consists of the file ``config/task.conf``.
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This file contains all the configuration variables (such as architecture, benchmarks, synthesis parameters, flow type etc.).
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A ``task`` is executed using the ``run-task`` command
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Lets create the OpenFPGA task from the template with above settings. Following code with create a directory/task named ``lab1`` from ``frac-lut-arch-explore`` template.
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.. code-block:: bash
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# create-task <new_task_dir_name> <template_name>
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create-task lab1 frac-lut-arch-explore
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tree lab1 # To check content of the copied task
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# lab1/
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# ├── config
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# │ └── task.conf
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# ├── k6_frac_N10_tileable.xml
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# ├── k6_N10_tileable.xml
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# └── vtr_benchmark_template_script.openfpga
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task.conf
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~~~~~~~~~
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``OpenFPGA_SHELL`` section defines common template script used in this flow.
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.. code-block:: bash
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:TASK_DIR}/vtr_benchmark_template_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
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vpr_route_chan_width=300
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.. code-block:: bash
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[ARCHITECTURES]
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arch0=${PATH:TASK_DIR}/k6_N10_tileable_dpram8K_dsp36_40nm.xml
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arch1=${PATH:TASK_DIR}/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml
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.. code-block:: bash
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[BENCHMARKS]
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bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v
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bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v
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bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v
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bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/sha.v
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OpenFPGA shell script
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~~~~~~~~~~~~~~~~~~~~~
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``*.openfpgashell`` script is simialr to TCL script for traditional FPGA CAD tools
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If you notice content of ``vtr_benchmark_template_script.openfpga`` file,
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it simply excutes the VPR tool. More commands are avaialble :ref:`_openfpga_commands`
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.. code-block:: bash
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# Execute VPR for architecture exploration
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \
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--route_chan_width ${VPR_ROUTE_CHAN_WIDTH} \
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--constant_net_method route
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exit
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Architecture Files
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~~~~~~~~~~~~~~~~~~
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Run OpenFPGA Task
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^^^^^^^^^^^^^^^^^
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.. code-block:: bash
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run-task lab1 # To excute the task
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Execute OpenFPGA Task
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^^^^^^^^^^^^^^^^^^^^^
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Analyze Results
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^^^^^^^^^^^^^^^
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.. code-block:: bash
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column -t -s, lab1/latest/task_result.csv | less -S
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.. code-block:: csv
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name ,TotalRunTime , clb_blocks ,total_wire_length
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00_memset_ , 1 , 31 , 2217
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01_memset_ , 6 , 25 , 2120
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00_diffeq_paj_convert_ , 16 , 368 , 43526
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01_diffeq_paj_convert_ , 45 , 276 , 38465
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00_diffeq_f_systemC_ , 16 , 354 , 37245
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01_diffeq_f_systemC_ , 42 , 262 , 32722
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00_sha1_ , 9 , 168 , 16099
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01_sha1_ , 14 , 153 , 15274
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