27 lines
676 B
Verilog
27 lines
676 B
Verilog
module ROM(
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output reg [7:0] rom_out,
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input [3:0] rom_in
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);
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always @(*)
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begin
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rom_out = 8'bx;
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case(rom_in)
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4'b0000: rom_out = 8'b0000_1001; //LDA
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4'b0001: rom_out = 8'b0001_1010; //ADD
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4'b0010: rom_out = 8'b0001_1011; //ADD
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4'b0011: rom_out = 8'b0010_1100; //SUB
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4'b0100: rom_out = 8'b1110_xxxx; //OUT
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4'b0101: rom_out = 8'b1111_xxxx; //HLT
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4'b0110: rom_out = 8'bxxxx_xxxx;
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4'b0111: rom_out = 8'bxxxx_xxxx;
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4'b1000: rom_out = 8'bxxxx_xxxx;
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4'b1001: rom_out = 8'b0001_0000;
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4'b1010: rom_out = 8'b0001_0100;
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4'b1011: rom_out = 8'b0001_1000;
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4'b1100: rom_out = 8'b0010_0000;
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endcase
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end
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endmodule
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