tangxifan 1ca1b0f3e9 [Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests		2021-09-22 15:58:05 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks	2021-07-02 17:28:17 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Test] Added a sample fabric key for 2-region QL memory bank	2021-09-22 11:25:16 -07:00
misc	[Script] Update yosys script using BRAMs	2021-04-27 21:44:27 -06:00
openfpga_arch	[Arch] Bug fix: wrong circuit model name was used for CCFF	2021-09-22 15:50:47 -07:00
openfpga_cell_library	[HDL] Temporarily disable WLR func in primitive HDL modeling	2021-09-20 17:07:51 -07:00
openfpga_shell_scripts	[Test] Bug fix	2021-06-29 18:51:28 -06:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_yosys_techlib	[Script] Add dff with active-low async reset to default yosys tech lib	2021-07-02 11:17:43 -06:00
regression_test_scripts	[Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests	2021-09-22 15:58:05 -07:00
scripts	Merge remote-tracking branch 'upstream/master'	2021-09-01 14:19:00 -07:00
tasks	[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level	2021-09-22 15:56:44 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Patch architecture due to missing mode bit definition	2021-07-02 11:41:29 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00