This website requires JavaScript.
Explore
Help
Sign In
riscv
/
OpenFPGA
mirror of
https://github.com/lnis-uofu/OpenFPGA.git
Watch
1
Star
0
Fork
You've already forked OpenFPGA
0
Code
Issues
Projects
Releases
Wiki
Activity
04eb6d3488
OpenFPGA
/
yosys
/
tests
/
sat
/
initval.ys
5 lines
62 B
Plaintext
Raw
Blame
History
read_verilog -sv initval.v
proc;;
sat -seq 10 -prove-asserts
Reference in New Issue
View Git Blame
Copy Permalink