tangxifan 0425b00af5 [engine] fixed a bug for frame-based protocols		2022-09-14 16:41:30 -07:00
..
annotation	[engine] now consider circuit model rather than switchId and SegmentId when identifying GSB structure similarity	2022-09-06 13:40:29 -07:00
base	[engine] now repack has a new option "--ignore_global_nets_on_pins"	2022-09-12 16:18:26 -07:00
fabric	[engine] fixed a bug for frame-based protocols	2022-09-14 16:41:30 -07:00
fpga_bitstream	[engine] syntax	2022-09-01 16:40:17 -07:00
fpga_sdc	[FPGA-SDC] Add a new option ``--no_time_stamp`` to all the commands	2022-01-25 15:51:28 -08:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports	2022-03-16 20:51:37 +08:00
mux_lib	[Engine] Support WLR port in OpenFPGA architecture file and fabric generator	2021-09-20 16:05:36 -07:00
repack	[engine] fixed a few bugs	2022-09-12 16:50:32 -07:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[engine] fixed a bug for frame-based protocols	2022-09-14 16:41:30 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	[engine] added command 'pcf2place' to openfpga	2022-07-28 11:30:36 -07:00