Tarachand Pagarani 3a587f663a copy yosys output file in case power analysis setting is off		2021-02-15 02:36:02 -08:00
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pro_blif.pl	now pro_blif.pl can accept customized clock name	2020-08-19 09:43:44 -06:00
run_formality.py	Updated formality python script	2019-09-27 14:00:57 -06:00
run_fpga_flow.py	copy yosys output file in case power analysis setting is off	2021-02-15 02:36:02 -08:00
run_fpga_task.conf	Updated to run with python3	2019-08-31 21:42:31 -06:00
run_fpga_task.py	[Flow] Support multi-user enviroment for running task	2021-02-07 22:11:04 -07:00
run_modelsim.py	BugFix : Relative path for refrence benchmark fixed	2020-04-25 20:16:17 -06:00