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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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temp-fix-ptc-plus-win-build
OpenFPGA
/
vpr
/
src
History
coolbreeze413
cf5092b7fe
Merge branch 'win32-build' into temp-fix-ptc-plus-win-build
2022-06-30 18:27:30 +05:30
..
analysis
add vpr8 libs and core engine for further integration
2020-01-03 16:14:42 -07:00
base
fix count of ',' logic and clear stringstream for string to int conversion
2022-06-30 18:06:32 +05:30
device
Disabled printing segment ids for non-channel nodes.
2020-11-23 17:07:28 +01:00
draw
correct missing rr_nodes usage to rr_graph obj
2020-02-04 16:48:15 -07:00
pack
[Tool] Borrow a quick fix from the VPR pull request
https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1656/files
2021-02-04 17:30:49 -07:00
place
header inclusions required for MinGW windows build
2022-06-29 07:03:38 +05:30
power
power estimation adapted to use RRGraph object
2020-02-01 12:26:42 -07:00
route
Fix tileable rr graph read/write issue.
2022-06-06 12:34:54 -07:00
tileable_rr_graph
[Engine] Clear up compiler warning in tileable rr_graph builder
2021-09-24 15:20:43 -07:00
timing
net delay adopt RRGraph object, compile with no errors
2020-02-01 22:38:21 -07:00
util
correct missing rr_nodes usage to rr_graph obj
2020-02-04 16:48:15 -07:00
main.cpp
add vpr8 libs and core engine for further integration
2020-01-03 16:14:42 -07:00