tangxifan 91627abe12 [FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided		2021-10-30 11:53:46 -07:00
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annotation	[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes	2021-04-24 14:53:29 -06:00
base	[Tool] Bug fix for testbench generation without self checking codes	2021-06-29 16:27:29 -06:00
fabric	[Tool] Fix a compiler warning due to uninitialized data structure	2021-06-18 16:20:13 -06:00
fpga_bitstream	[Tool] Add postfix removal support in write_io_mapping command	2021-06-18 16:13:50 -06:00
fpga_sdc	Merge branch 'master' into dev	2021-06-23 09:15:03 -06:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided	2021-10-30 11:53:46 -07:00
mux_lib	[Tool] Support superLUT circuit model in core engine	2021-02-09 20:23:05 -07:00
repack	[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes	2021-04-24 14:53:29 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time	2021-06-29 09:56:04 -06:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	[Tool] Add --version to openfpga shell option and a command to openfpga shell	2021-01-27 16:03:46 -07:00