tangxifan 47cb1cc2d4 [Test] Deploy synthesizable verilog test to CI		2021-02-17 16:13:15 -07:00
..
basic_reg_test.sh	[Test] Remove quicklogic test from basic tests	2021-02-16 12:29:10 -07:00
fpga_bitstream_reg_test.sh	[Test] Move regression test scripts from workflow to openfpga_flow	2021-02-16 11:55:47 -07:00
fpga_sdc_reg_test.sh	[Test] Move regression test scripts from workflow to openfpga_flow	2021-02-16 11:55:47 -07:00
fpga_spice_reg_test.sh	[Test] Move regression test scripts from workflow to openfpga_flow	2021-02-16 11:55:47 -07:00
fpga_verilog_reg_test.sh	[Test] Deploy synthesizable verilog test to CI	2021-02-17 16:13:15 -07:00
quicklogic_reg_test.sh	[Test] Move regression test scripts from workflow to openfpga_flow	2021-02-16 11:55:47 -07:00