tangxifan 47cb1cc2d4 [Test] Deploy synthesizable verilog test to CI		2021-02-17 16:13:15 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture	2021-02-09 15:41:21 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	[Cleanup] Removed deadcode	2021-02-03 10:35:14 -07:00
openfpga_arch	Merge pull request #227 from watcag/master	2021-02-17 10:11:34 -07:00
openfpga_cell_library	Merge pull request #227 from watcag/master	2021-02-17 10:11:34 -07:00
openfpga_shell_scripts	Merge pull request #227 from watcag/master	2021-02-17 10:11:34 -07:00
openfpga_simulation_settings	[Flow] Update simulation settings for multiple clock to allow unique clock port name	2021-01-15 10:35:43 -07:00
regression_test_scripts	[Test] Deploy synthesizable verilog test to CI	2021-02-17 16:13:15 -07:00
scripts	Merge pull request #227 from watcag/master	2021-02-17 10:11:34 -07:00
tasks	Merge pull request #227 from watcag/master	2021-02-17 10:11:34 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Bug fix in the example arch with super LUT	2021-02-09 15:52:22 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00