tangxifan 8ab090651a [FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports		2022-03-16 20:51:37 +08:00
..
build.yml	build.yml flow is updated with basic_reg_yosys_only_test	2022-01-14 15:45:22 +05:00
docker.yml	[Bugfix] docker CI build	2021-10-20 14:50:17 -06:00
install_dependencies_build.sh	[FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports	2022-03-16 20:51:37 +08:00
install_dependencies_run.sh	add wget to list of dependencies	2021-10-08 03:22:30 +05:30
install_dependency_old.sh	Fix dependency script reference in old build	2021-01-25 11:58:35 -07:00
labeler.yml	Add docker build workflow and fix submodule issues.	2020-12-22 17:37:14 -07:00
patch_updater.yml	[CI] Update patch updater due to release v1.1.0	2022-02-20 23:32:11 -08:00