tangxifan 8aa2647878 [Script] Bug fix in slow clock frequency in shift register chain contraints		2021-10-06 16:49:01 -07:00
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auto_shift_register_sim_openfpga.xml	[Flow] Modify simulation setting example for QuickLogic memory bank using separated clks for BL and WL shift registers	2021-10-01 16:52:06 -07:00
auto_sim_openfpga.xml	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00
fixed_4clock_sim_openfpga.xml	[Arch] Add more comments on the 4 clock simulation setting file	2021-02-22 11:04:34 -07:00
fixed_8clock_sim_openfpga.xml	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
fixed_shift_register_sim_openfpga.xml	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
fixed_sim_openfpga.xml	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00