259 lines
10 KiB
XML
259 lines
10 KiB
XML
<?xml version="1.0"?>
|
|
<!--
|
|
Architecture with no fracturable LUTs
|
|
|
|
- 40 nm technology
|
|
- General purpose logic block:
|
|
K = 4, N = 4
|
|
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
|
|
|
|
Details on Modelling:
|
|
|
|
Based on flagship k6_frac_N10_mem32K_40nm.xml architecture. This architecture has no fracturable LUTs nor any heterogeneous blocks.
|
|
|
|
|
|
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
|
|
-->
|
|
<architecture>
|
|
<models>
|
|
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
|
<model name="io_inpad">
|
|
<output_ports>
|
|
<port name="inpad"/>
|
|
</output_ports>
|
|
</model>
|
|
<model name="io_outpad">
|
|
<input_ports>
|
|
<port name="outpad"/>
|
|
</input_ports>
|
|
</model>
|
|
</models>
|
|
<tiles>
|
|
<tile name="hybrid_io_tile_center" area="0">
|
|
<sub_tile name="fpga_input_center" capacity="6">
|
|
<equivalent_sites>
|
|
<site pb_type="fpga_input"/>
|
|
</equivalent_sites>
|
|
<output name="inpad" num_pins="1"/>
|
|
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
|
<pinlocations pattern="custom">
|
|
<loc side="left">fpga_input_center[1:0].inpad</loc>
|
|
<loc side="top">fpga_input_center[3:2].inpad</loc>
|
|
<loc side="right">fpga_input_center[4:4].inpad</loc>
|
|
<loc side="bottom">fpga_input_center[5:5].inpad</loc>
|
|
</pinlocations>
|
|
</sub_tile>
|
|
<sub_tile name="fpga_output_center" capacity="4">
|
|
<equivalent_sites>
|
|
<site pb_type="fpga_output"/>
|
|
</equivalent_sites>
|
|
<input name="outpad" num_pins="1"/>
|
|
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
|
<pinlocations pattern="custom">
|
|
<loc side="left">fpga_output_center[1:0].outpad</loc>
|
|
<loc side="top"/>
|
|
<loc side="right">fpga_output_center[3:2].outpad</loc>
|
|
<loc side="bottom"/>
|
|
</pinlocations>
|
|
</sub_tile>
|
|
</tile>
|
|
<tile name="hybrid_io_tile" area="0">
|
|
<sub_tile name="fpga_input" capacity="4">
|
|
<equivalent_sites>
|
|
<site pb_type="fpga_input"/>
|
|
</equivalent_sites>
|
|
<output name="inpad" num_pins="1"/>
|
|
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
|
<pinlocations pattern="custom">
|
|
<loc side="left"> fpga_input.inpad</loc>
|
|
<loc side="top"> fpga_input.inpad</loc>
|
|
<loc side="right"> fpga_input.inpad</loc>
|
|
<loc side="bottom"> fpga_input.inpad</loc>
|
|
</pinlocations>
|
|
</sub_tile>
|
|
<sub_tile name="fpga_output" capacity="2">
|
|
<equivalent_sites>
|
|
<site pb_type="fpga_output"/>
|
|
</equivalent_sites>
|
|
<input name="outpad" num_pins="1"/>
|
|
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
|
<pinlocations pattern="custom">
|
|
<loc side="left"> fpga_output.outpad</loc>
|
|
<loc side="top"> fpga_output.outpad</loc>
|
|
<loc side="right"> fpga_output.outpad</loc>
|
|
<loc side="bottom"> fpga_output.outpad</loc>
|
|
</pinlocations>
|
|
</sub_tile>
|
|
</tile>
|
|
<tile name="clb" area="53894">
|
|
<sub_tile name="clb">
|
|
<equivalent_sites>
|
|
<site pb_type="clb"/>
|
|
</equivalent_sites>
|
|
<input name="I" num_pins="10" equivalent="full"/>
|
|
<output name="O" num_pins="4" equivalent="none"/>
|
|
<clock name="clk" num_pins="1"/>
|
|
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
|
|
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
|
|
</fc>
|
|
<pinlocations pattern="spread"/>
|
|
</sub_tile>
|
|
</tile>
|
|
</tiles>
|
|
<!-- ODIN II specific config ends -->
|
|
<!-- Physical descriptions begin -->
|
|
<layout tileable="true">
|
|
<auto_layout aspect_ratio="1.0">
|
|
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
|
<perimeter type="io" priority="100"/>
|
|
<corners type="EMPTY" priority="101"/>
|
|
<!--Fill with 'clb'-->
|
|
<fill type="clb" priority="10"/>
|
|
</auto_layout>
|
|
<fixed_layout name="2x2" width="4" height="4">
|
|
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
|
<perimeter type="hybrid_io_tile" priority="100"/>
|
|
<corners type="EMPTY" priority="101"/>
|
|
<!--Fill with 'clb'-->
|
|
<fill type="clb" priority="10"/>
|
|
</fixed_layout>
|
|
<fixed_layout name="3x3" width="5" height="5">
|
|
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
|
<perimeter type="hybrid_io_tile" priority="100"/>
|
|
<single type="hybrid_io_tile_center" x="2" y="2" priority="100"/>
|
|
<corners type="EMPTY" priority="101"/>
|
|
<!--Fill with 'clb'-->
|
|
<fill type="clb" priority="10"/>
|
|
</fixed_layout>
|
|
</layout>
|
|
<device>
|
|
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
|
|
<area grid_logic_tile_area="0"/>
|
|
<chan_width_distr>
|
|
<x distr="uniform" peak="1.000000"/>
|
|
<y distr="uniform" peak="1.000000"/>
|
|
</chan_width_distr>
|
|
<switch_block type="wilton" fs="3"/>
|
|
<connection_block input_switch_name="ipin_cblock"/>
|
|
</device>
|
|
<switchlist>
|
|
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
|
|
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
|
|
</switchlist>
|
|
<segmentlist>
|
|
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
|
|
<mux name="0"/>
|
|
<sb type="pattern">1 1 1 1 1</sb>
|
|
<cb type="pattern">1 1 1 1</cb>
|
|
</segment>
|
|
</segmentlist>
|
|
<complexblocklist>
|
|
<pb_type name="fpga_input">
|
|
<output name="inpad" num_pins="1"/>
|
|
<mode name="physical" disable_packing="true">
|
|
<pb_type name="iopad" blif_model=".subckt io_inpad" num_pb="1">
|
|
<output name="inpad" num_pins="1"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="inpad" input="iopad.inpad" output="fpga_input.inpad"/>
|
|
</interconnect>
|
|
</mode>
|
|
<mode name="inpad">
|
|
<pb_type name="inpad" blif_model=".input" num_pb="1">
|
|
<output name="inpad" num_pins="1"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="inpad" input="inpad.inpad" output="fpga_input.inpad">
|
|
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="fpga_input.inpad"/>
|
|
</direct>
|
|
</interconnect>
|
|
</mode>
|
|
</pb_type>
|
|
<pb_type name="fpga_output">
|
|
<input name="outpad" num_pins="1"/>
|
|
<mode name="physical" disable_packing="true">
|
|
<pb_type name="iopad" blif_model=".subckt io_outpad" num_pb="1">
|
|
<input name="outpad" num_pins="1"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="outpad" input="fpga_output.outpad" output="iopad.outpad"/>
|
|
</interconnect>
|
|
</mode>
|
|
<mode name="outpad">
|
|
<pb_type name="outpad" blif_model=".output" num_pb="1">
|
|
<input name="outpad" num_pins="1"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="outpad" input="fpga_output.outpad" output="outpad.outpad"/>
|
|
</interconnect>
|
|
</mode>
|
|
</pb_type>
|
|
<pb_type name="clb">
|
|
<input name="I" num_pins="10" equivalent="full"/>
|
|
<output name="O" num_pins="4" equivalent="none"/>
|
|
<clock name="clk" num_pins="1"/>
|
|
<pb_type name="fle" num_pb="4">
|
|
<input name="in" num_pins="4"/>
|
|
<output name="out" num_pins="1"/>
|
|
<clock name="clk" num_pins="1"/>
|
|
<!-- 4-LUT mode definition begin -->
|
|
<mode name="n1_lut4">
|
|
<!-- Define 4-LUT mode -->
|
|
<pb_type name="ble4" num_pb="1">
|
|
<input name="in" num_pins="4"/>
|
|
<output name="out" num_pins="1"/>
|
|
<clock name="clk" num_pins="1"/>
|
|
<!-- Define LUT -->
|
|
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
|
|
<input name="in" num_pins="4" port_class="lut_in"/>
|
|
<output name="out" num_pins="1" port_class="lut_out"/>
|
|
<!-- LUT timing using delay matrix -->
|
|
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
|
|
261e-12
|
|
261e-12
|
|
261e-12
|
|
261e-12
|
|
</delay_matrix>
|
|
</pb_type>
|
|
<!-- Define flip-flop -->
|
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
|
<input name="D" num_pins="1" port_class="D"/>
|
|
<output name="Q" num_pins="1" port_class="Q"/>
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
|
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
|
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
|
|
<direct name="direct2" input="lut4.out" output="ff.D">
|
|
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
|
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
|
|
</direct>
|
|
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
|
|
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
|
|
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
|
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
|
|
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
|
|
</mux>
|
|
</interconnect>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="direct1" input="fle.in" output="ble4.in"/>
|
|
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
|
|
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
|
|
</interconnect>
|
|
</mode>
|
|
</pb_type>
|
|
<interconnect>
|
|
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
|
|
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
|
|
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
|
|
</complete>
|
|
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
|
|
</complete>
|
|
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
|
|
</interconnect>
|
|
</pb_type>
|
|
</complexblocklist>
|
|
</architecture>
|