34 lines
1.1 KiB
Plaintext
34 lines
1.1 KiB
Plaintext
# Run VPR for the 'and' design
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric ${OPENFPGA_BUILD_FABRIC_OPTION} #--verbose
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# Write gsb to XML
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write_gsb_to_xml --file gsb_xml --verbose ${OPENFPGA_WRITE_GSB_OPTION}
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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