OpenFPGA/openfpga_flow/misc/qlf_yosys.ys

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# Yosys synthesis script for ${TOP_MODULE}
plugin -i ql-qlf
# Read verilog files
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
synth_ql -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}
write_verilog -noattr -nohex ${OUTPUT_VERILOG}