Aur??Lien ALACCHI 3ef0047f3e Add disclaimer in architecture file		2021-01-29 09:22:23 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	Add required files for LUTRAM integration and testing	2021-01-27 14:56:41 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow	2021-01-08 07:08:24 -08:00
openfpga_arch	Add required files for LUTRAM integration and testing	2021-01-27 14:56:41 -07:00
openfpga_cell_library	Add required files for LUTRAM integration and testing	2021-01-27 14:56:41 -07:00
openfpga_shell_scripts	[Script] Use pin constraints in template script	2021-01-19 17:42:25 -07:00
openfpga_simulation_settings	[Flow] Update simulation settings for multiple clock to allow unique clock port name	2021-01-15 10:35:43 -07:00
scripts	[Regression] Upgraded runtime enviroment to python3.8	2021-01-26 16:40:45 -07:00
tasks	Add task for lutram	2021-01-27 15:57:58 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	Add disclaimer in architecture file	2021-01-29 09:22:23 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00