50 lines
1.2 KiB
Bash
Executable File
50 lines
1.2 KiB
Bash
Executable File
#!/bin/bash
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# Regression test version 1.0
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# Set variables
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my_pwd=$PWD
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fpga_flow_scripts="${my_pwd}/fpga_flow/scripts"
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vpr_path="${my_pwd}/vpr7_x2p/vpr"
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benchmark="test_modes"
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include_netlists="_include_netlists.v"
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compiled_file="compiled_$benchmark"
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tb_formal_postfix="_top_formal_verification_random_tb"
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verilog_dirname="${vpr_path}/${benchmark}_Verilog"
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log_file="${benchmark}_sim.log"
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new_reg_sh="${PWD}/ERI_demo/my_eri_demo.sh"
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template_sh="${PWD}/ERI_demo/eri_demo.sh"
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# Remove former log file
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rm -f $log_file
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rm -f $compiled_file
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# Rewite script
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cd $fpga_flow_scripts
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perl rewrite_path_in_file.pl -i $template_sh -o $new_reg_sh
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cd $my_pwd
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# Start the script -> run the fpga generation -> run the simulation -> check the log file
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source $new_reg_sh # Leave us in vpr folder
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cd $my_pwd
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iverilog -o $compiled_file ${verilog_dirname}/SRC/${benchmark}${include_netlists} -s ${benchmark}${tb_formal_postfix}
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vvp $compiled_file -j 64 >> $log_file
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result=`grep "Succeed" $log_file`
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if ["$result" = ""]; then
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result=`grep "Failed" $log_file`
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if ["$result" = ""]; then
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echo "Unexpected error, Verification didn't run"
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exit 1
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else
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echo "Verification failed"
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exit 2
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fi
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else
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echo "Verification succeed"
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gtkwave ${benchmark}_formal.vcd &
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fi
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