# Benchmark "pip_add" written by ABC on Fri Dec 7 14:18:10 2018 .model pip_add .inputs rst clk a_0 a_1 a_2 a_3 a_4 a_5 a_6 a_7 b_0 b_1 b_2 b_3 b_4 b_5 b_6 \ b_7 cin .outputs sumout_0 sumout_1 sumout_2 sumout_3 sumout_4 sumout_5 sumout_6 \ sumout_7 cout .latch n57 reg0_a[0] re clk 0 .latch n62 reg0_a[1] re clk 0 .latch n67 reg0_a[2] re clk 0 .latch n72 reg0_a[3] re clk 0 .latch n77 reg0_a[4] re clk 0 .latch n82 reg0_a[5] re clk 0 .latch n87 reg0_a[6] re clk 0 .latch n92 reg0_a[7] re clk 0 .latch n97 reg1_a[0] re clk 0 .latch n102 reg1_a[1] re clk 0 .latch n107 reg1_a[2] re clk 0 .latch n112 reg1_a[3] re clk 0 .latch n117 reg1_a[4] re clk 0 .latch n122 reg1_a[5] re clk 0 .latch n127 reg1_a[6] re clk 0 .latch n132 reg1_a[7] re clk 0 .latch n137 reg2_a[0] re clk 0 .latch n142 reg2_a[1] re clk 0 .latch n147 reg2_a[2] re clk 0 .latch n152 reg2_a[3] re clk 0 .latch n157 reg2_a[4] re clk 0 .latch n162 reg2_a[5] re clk 0 .latch n167 reg2_a[6] re clk 0 .latch n172 reg2_a[7] re clk 0 .latch n177 reg0_b[0] re clk 0 .latch n182 reg0_b[1] re clk 0 .latch n187 reg0_b[2] re clk 0 .latch n192 reg0_b[3] re clk 0 .latch n197 reg0_b[4] re clk 0 .latch n202 reg0_b[5] re clk 0 .latch n207 reg0_b[6] re clk 0 .latch n212 reg0_b[7] re clk 0 .latch n217 reg1_b[0] re clk 0 .latch n222 reg1_b[1] re clk 0 .latch n227 reg1_b[2] re clk 0 .latch n232 reg1_b[3] re clk 0 .latch n237 reg1_b[4] re clk 0 .latch n242 reg1_b[5] re clk 0 .latch n247 reg1_b[6] re clk 0 .latch n252 reg1_b[7] re clk 0 .latch n257 reg2_b[0] re clk 0 .latch n262 reg2_b[1] re clk 0 .latch n267 reg2_b[2] re clk 0 .latch n272 reg2_b[3] re clk 0 .latch n277 reg2_b[4] re clk 0 .latch n282 reg2_b[5] re clk 0 .latch n287 reg2_b[6] re clk 0 .latch n292 reg2_b[7] re clk 0 .latch n297 reg0_cin re clk 0 .latch n302 reg1_cin re clk 0 .latch n307 reg2_cin re clk 0 .latch n312 cout re clk 0 .latch n316 sumout_0 re clk 0 .latch n320 sumout_1 re clk 0 .latch n324 sumout_2 re clk 0 .latch n328 sumout_3 re clk 0 .latch n332 sumout_4 re clk 0 .latch n336 sumout_5 re clk 0 .latch n340 sumout_6 re clk 0 .latch n344 sumout_7 re clk 0 .names reg2_a[6] reg2_b[6] n212_1 rst n340 0000 1 0110 1 1010 1 1100 1 .names n216 n213 reg2_a[5] reg2_b[5] n212_1 000- 1 00-0 1 --00 1 .names n215 reg2_a[2] reg2_b[2] reg2_a[3] reg2_b[3] n214 n213 1111-- 1 111-1- 1 11-1-0 1 11--10 1 1-11-0 1 1-1-10 1 1--11- 1 .names reg2_a[1] reg2_cin reg2_a[0] reg2_b[0] reg2_b[1] n214 000-- 1 00-0- 1 0-00- 1 0---0 1 -00-0 1 -0-00 1 --000 1 .names reg2_a[4] reg2_b[4] n215 01 1 10 1 .names reg2_a[4] reg2_b[4] n216 11 1 .names reg2_a[7] reg2_b[7] n218 rst n344 0000 1 0110 1 1010 1 1100 1 .names n213 n216 reg2_a[6] reg2_a[5] reg2_b[5] reg2_b[6] n218 0000-- 1 000-0- 1 00-0-0 1 00--00 1 --000- 1 --0--0 1 ---000 1 .names a_0 rst n57 10 1 .names a_1 rst n62 10 1 .names a_2 rst n67 10 1 .names a_3 rst n72 10 1 .names a_4 rst n77 10 1 .names a_5 rst n82 10 1 .names a_6 rst n87 10 1 .names a_7 rst n92 10 1 .names reg0_a[0] rst n97 10 1 .names reg0_a[1] rst n102 10 1 .names reg0_a[2] rst n107 10 1 .names reg0_a[3] rst n112 10 1 .names reg0_a[4] rst n117 10 1 .names reg0_a[5] rst n122 10 1 .names reg0_a[6] rst n127 10 1 .names reg0_a[7] rst n132 10 1 .names reg1_a[0] rst n137 10 1 .names reg1_a[1] rst n142 10 1 .names reg1_a[2] rst n147 10 1 .names reg1_a[3] rst n152 10 1 .names reg1_a[4] rst n157 10 1 .names reg1_a[5] rst n162 10 1 .names reg1_a[6] rst n167 10 1 .names reg1_a[7] rst n172 10 1 .names b_0 rst n177 10 1 .names b_1 rst n182 10 1 .names b_2 rst n187 10 1 .names b_3 rst n192 10 1 .names b_4 rst n197 10 1 .names b_5 rst n202 10 1 .names b_6 rst n207 10 1 .names b_7 rst n212 10 1 .names reg0_b[0] rst n217 10 1 .names reg0_b[1] rst n222 10 1 .names reg0_b[2] rst n227 10 1 .names reg0_b[3] rst n232 10 1 .names reg0_b[4] rst n237 10 1 .names reg0_b[5] rst n242 10 1 .names reg0_b[6] rst n247 10 1 .names reg0_b[7] rst n252 10 1 .names reg1_b[0] rst n257 10 1 .names reg1_b[1] rst n262 10 1 .names reg1_b[2] rst n267 10 1 .names reg1_b[3] rst n272 10 1 .names reg1_b[4] rst n277 10 1 .names reg1_b[5] rst n282 10 1 .names reg1_b[6] rst n287 10 1 .names reg1_b[7] rst n292 10 1 .names cin rst n297 10 1 .names reg0_cin rst n302 10 1 .names reg1_cin rst n307 10 1 .names rst reg2_a[7] reg2_b[7] n218 n312 011- 1 01-0 1 0-10 1 .names reg2_cin reg2_a[0] reg2_b[0] rst n316 0010 1 0100 1 1000 1 1110 1 .names reg2_a[1] reg2_b[1] rst reg2_cin reg2_a[0] reg2_b[0] n320 00011- 1 0001-1 1 000-11 1 01000- 1 0100-0 1 010-00 1 10000- 1 1000-0 1 100-00 1 11011- 1 1101-1 1 110-11 1 .names reg2_a[2] reg2_b[2] n214 rst n324 0000 1 0110 1 1010 1 1100 1 .names reg2_a[3] reg2_b[3] n275 rst n328 0000 1 0110 1 1010 1 1100 1 .names reg2_a[2] reg2_b[2] n214 n275 00- 1 0-1 1 -01 1 .names reg2_a[5] reg2_b[5] rst n216 n213 n336 0001- 1 000-1 1 01000 1 10000 1 1101- 1 110-1 1 .names n215 rst reg2_a[3] reg2_b[3] n275 n332 0011- 1 001-0 1 00-10 1 1000- 1 100-1 1 10-01 1 .end