% This should the last document processed by sphinx (to resolve all citations). hence
% the z_ prefix to the filename

@INPROCEEDINGS{XTang_ICCD_2015,
author={X. Tang and P. Gaillardon and G. De Micheli},
booktitle={2015 33rd IEEE International Conference on Computer Design (ICCD)},
title={FPGA-SPICE: A simulation-based power estimation framework for FPGAs},
year={2015},
volume={},
number={},
pages={696-703},
keywords={circuit simulation;field programmable gate arrays;logic design;power consumption;SPICE;table lookup;flip-flops;global routing architecture;circuit elements;grid-level testbenches;full-chip-level testbenches;component-level testbenches;architectural description language;LUTs;FPGAs routing multiplexers;look up tables;power consumption;analytical power models;probabilistic activity estimation;field programmable gate array;simulation-based power estimation framework;FPGA-SPICE;Field programmable gate arrays;Routing;Integrated circuit modeling;Estimation;SPICE;Table lookup},
doi={10.1109/ICCD.2015.7357183},
ISSN={},
month={Oct},}

@book{VBetz_Book_1999,
 editor = {Betz, Vaughn and Rose, Jonathan and Marquardt, Alexander},
 title = {Architecture and CAD for Deep-Submicron FPGAs},
 year = {1999},
 isbn = {0792384601},
 publisher = {Kluwer Academic Publishers},
 address = {Norwell, MA, USA},
} 

@inproceedings{JLuu_FPGA_2011,
	author = {Luu, Jason and Anderson, Jason Helge and Rose, Jonathan Scott},
	title = {{Architecture Description and Packing for Logic Blocks with Hierarchy, Modes and Complex Interconnect}},
	booktitle = {Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays},
	series = {FPGA '11},
	year = {2011},
	isbn = {978-1-4503-0554-9},
	location = {Monterey, CA, USA},
	pages = {227--236},
	numpages = {10},
	url = {http://doi.acm.org/10.1145/1950413.1950457},
	doi = {10.1145/1950413.1950457},
	acmid = {1950457},
	publisher = {ACM},
	address = {New York, NY, USA},
	keywords = {architecture description language, clustering, complex block, configurable memory, configurable multiplier, fpga, hard logic cluster, logic block, logic cluster, packing, soft logic cluster, splitting},
} 

@INPROCEEDINGS{JGoeders_FPT_2012,
	author={J. B. Goeders and S. J. E. Wilton},
	booktitle={2012 International Conference on Field-Programmable Technology},
	title={{VersaPower: Power Estimation for Diverse FPGA Architectures}},
	year={2012},
	pages={229-234},
	keywords={CMOS integrated circuits;SPICE;computer architecture;field programmable gate arrays;logic CAD;CMOS technology;HDL;SPICE;VPR;VersaPower;Versatile Place and Route 6.0;academic FPGA CAD tool;complex logic block;diverse FPGA architecture;field programmable gate array;fracturable look-up table;power consumption;power estimation;size 130 nm;size 22 nm;size 45 nm;Capacitance;Field programmable gate arrays;Multiplexing;Solid modeling;Table lookup;Transistors;Wires},
	doi={10.1109/FPT.2012.6412139},
	month={Dec},}

@inproceedings{JRose_FPGA_2012,
   author = {Rose, Jonathan and Luu, Jason and Yu, Chi Wai and Densmore, Opal and Goeders, Jeffrey and Somerville, Andrew and Kent, Kenneth B. and Jamieson, Peter and Anderson, Jason},
   title = {{The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing}},
   booktitle = {Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays},
   series = {FPGA '12},
   year = {2012},
   isbn = {978-1-4503-1155-7},
   location = {Monterey, California, USA},
   pages = {77--86},
   numpages = {10},
   url = {http://doi.acm.org/10.1145/2145694.2145708},
   doi = {10.1145/2145694.2145708},
   acmid = {2145708},
   publisher = {ACM},
   address = {New York, NY, USA},
   keywords = {CAD, FPGA, architecture},
} 

@ARTICLE{XTang_TVLSI_2019,
  author={X. Tang and E. Giacomin and G. D. Micheli and P. Gaillardon},
  journal={{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}},
  title={{FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs}},
  year={2019},
  volume={27},
  number={3},
  pages={637-650},
  doi={10.1109/TVLSI.2018.2883923},
  ISSN={1063-8210},
  month={March},
}

@INPROCEEDINGS{XTang_FPL_2019,
author={X. Tang and E. Giacomin and A. Alacchi and B. Chauviere and P. Gaillardon},
booktitle={2019 29th International Conference on Field Programmable Logic and Applications (FPL)},
title={OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs},
year={2019},
volume={},
number={},
pages={367-374},
keywords={field programmable gate arrays;logic design;reconfigurable architectures;software prototyping;OpenFPGA;FPGA architectures;semicustom design;XML-to-Prototype design flow;Verilog netlists;FPGA fabric;XML language;VTR framework;production-ready layouts;fully-optimized commercial products;data processing applications;Field Programmable Gate Arrays;programmable accelerators;computing systems;Verilog-to-Bitstream generator;Field programmable gate arrays;Computer architecture;Hardware design languages;XML;Microprocessors;Layout;Libraries;FPGA;Verilog generator;Bitstream generation;Semi Custom Designed FPGA},
doi={10.1109/FPL.2019.00065},
ISSN={1946-147X},
month={Sep.},}

@INPROCEEDINGS{XTang_FPT_2019,
author={X. Tang and E. Giacomin and A. Alacchi and P. Gaillardon},  
booktitle={2019 International Conference on Field-Programmable Technology (ICFPT)}, 
title={A Study on Switch Block Patterns for Tileable FPGA Routing Architectures},
year={2019},
volume={},
number={},
doi={10.1109/ICFPT47387.2019.00039},
pages={247-250},}

@ARTICLE{XTang_ieeemicro_2020,  author={Tang, Xifan and Giacomin, Edouard and Chauviere, Baudouin and Alacchi, Aurélien and Gaillardon, Pierre-Emmanuel},  journal={IEEE Micro},   title={OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs},   year={2020},  volume={40},  number={4},  pages={41-48},  doi={10.1109/MM.2020.2995854}}

@article{XTang_woset_2020,
  title={OpenFPGA: Towards Automated Prototyping for Versatile FPGAs},
  author={Tang, Xifan and Gore, Ganesh and Giacomin, Edouard and Alacchi, Aur{\'e}lien and Chauviere, Baudouin and Gaillardon, Pierre-Emmanuel},
  journal={Workshop on Open-Source EDA Technology},
  year={2020}
}

@inproceedings{GGore_ispd_2021,
author = {Gore, Ganesh and Tang, Xifan and Gaillardon, Pierre-Emmanuel},
title = {A Scalable and Robust Hierarchical Floorplanning to Enable 24-Hour Prototyping for 100k-LUT FPGAs},
year = {2021},
isbn = {9781450383004},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
url = {https://doi.org/10.1145/3439706.3447047},
doi = {10.1145/3439706.3447047},
abstract = {Physical design for Field Programmable Gate Array (FPGA) is challenging and time-consuming, primarily due to the use of a full-custom approach for aggressively optimize Performance, Power and Area (P.P.A.) of the FPGA design. The growing number of FPGA applications demands novel architectures and shorter development cycles. The use of an automated toolchain is essential to reduce end-to-end development time. This paper presents scalable and adaptive hierarchical floorplanning strategies to significantly reduce the physical design runtime and enable millions-of-LUT FPGA layout implementations using standard ASIC toolchains. This approach mainly exploits the regularity of the design and performs necessary feedthrough creations for global and clock nets to eliminate any requirement of global optimizations. To validate this approach, we implemented full-chip layouts for modern FPGA fabric with logic capacity ranging from 40 to 100k LUTs using a commercial 12nm technology. Our results show that the physical implementation of a 128k-LUT FPGA fabric can be achieved within 24-hours, which has not been demonstrated by any previous work. Compared to previous work, the runtime reduction of 8x is obtained for implementing 2.5k LUTs FPGA device.},
booktitle = {Proceedings of the 2021 International Symposium on Physical Design},
pages = {135–142},
numpages = {8},
keywords = {reconfigurable computing, hierarchical design, physical design, fpga design},
location = {Virtual Event, USA},
series = {ISPD '21}
}