# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configuration file for running experiments # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs # Each job execute fpga_flow script on combination of architecture & benchmark # timeout_each_job is timeout for each job # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = [GENERAL] run_engine=openfpga_shell openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif [SYNTHESIS_PARAM] bench0_top = top bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= vpr_fpga_verilog_formal_verification_top_netlist=