#read design 
read_verilog -nolatches ../vpr7_x2p/vpr/Circuits/fifo_1bit.v

# synth 
hierarchy -top fifo_1bit
proc

# Tech map 
techmap -D NO_LUT -map ./techlibs/common/adff2dff.v
synth -top fifo_1bit -flatten  
clean

abc -lut 6

synth -run check

opt_clean -purge
write_blif ../vpr7_x2p/vpr/Circuits/fifo_1bit.blif